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Volumn , Issue , 2005, Pages 222-227

A side-channel leakage free coprocessor IC in 0.18μm CMOS for embedded AES-based cryptographic and biometric processing

Author keywords

Countermeasure; Differential Power Analysis; Encryption; Security IC; Side Channel Attack; Smart Card

Indexed keywords

CRYPTOGRAPHY; EMBEDDED SYSTEMS; ENERGY UTILIZATION; GATES (TRANSISTOR); SMART CARDS; STANDARDS;

EID: 27944462240     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1065579.1065639     Document Type: Conference Paper
Times cited : (55)

References (9)
  • 2
    • 4444331720 scopus 로고    scopus 로고
    • Security as a new dimension in embedded system design
    • P. Kocher, R. Lee, G. McGraw, A. Raghunathan and S. Ravi, "Security as a New Dimension in Embedded System Design," DAC, pp. 753-760, 2004.
    • (2004) DAC , pp. 753-760
    • Kocher, P.1    Lee, R.2    McGraw, G.3    Raghunathan, A.4    Ravi, S.5
  • 4
    • 3042604811 scopus 로고    scopus 로고
    • A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
    • K. Tiri and I. Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation," DATE, pp. 246-251, 2004.
    • (2004) DATE , pp. 246-251
    • Tiri, K.1    Verbauwhede, I.2
  • 5
    • 27944509716 scopus 로고    scopus 로고
    • A digital design flow for secure integrated circuits
    • submitted
    • K. Tiri and I. Verbauwhede, "A Digital Design Flow for Secure Integrated Circuits," submitted IEEE TCAD.
    • IEEE TCAD
    • Tiri, K.1    Verbauwhede, I.2
  • 6
    • 84902478964 scopus 로고    scopus 로고
    • Piace and route for secure standard cell design
    • K.. Tiri and I. Verbauwhede, "Piace and Route for Secure Standard Cell Design," CARDIS, pp. 143-158, 2004.
    • (2004) CARDIS , pp. 143-158
    • Tiri, K.1    Verbauwhede, I.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.