Characteristics of gate-all-around twin poly-Si nanowire thin-film transistors

IEEE Electron Device Letters

Volumn 30, Issue 2, 2009, Pages 139-141

  Sheu, Jeng Tzong ^a   Huang, Po Chun ^a   Sheu, Tzu Shiun ^a   Chen, Chen Chia ^a   Chen, Lu An ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Gate all around (GAA); Nanowire (NW); Plasma treatment; Short channel effects (SCEs); Thin film transistor (TFT)

Indexed keywords

ELECTRIC WIRE; GALLIUM ALLOYS; GATES (TRANSISTOR); NANOWIRES; PLASMA APPLICATIONS; PLASMAS; POLYSILICON; SEMICONDUCTING ORGANIC COMPOUNDS; THIN FILM DEVICES; THIN FILM TRANSISTORS; TRANSISTORS;

GATE-ALL-AROUND (GAA); NANOWIRE (NW); PLASMA TREATMENT; SHORT-CHANNEL EFFECTS (SCES); THIN-FILM TRANSISTOR (TFT);

MOSFET DEVICES;

EID: 59649117186     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2009956     Document Type: Article

References (17)

1. T. Aoyama, K. Ogawa, Y. Mochizuki, and N. Konishi, "Inverse staggered poly-Si and amorphous Si double structure TFTs for LCD panels with peripheral driver circuits integration," IEEE Trans. Electron Devices, vol. 43, no. 5, pp. 701-705, May 1996.
2. K. R. Olasupo and M. K. Hatalis, "Leakage current mechanism in submicron polysilicon thin-film transistors," IEEE Trans. Electron Devices, vol. 43, no. 8, pp. 1218-1223, Aug. 1996.
3. J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, "Conductivity behavior in polycrystalline semiconductor thin film transistors," J. Appl. Phys., vol. 53, no. 2, pp. 1193-1202, Feb. 1982.
4. N. Yamauchi, J. J. Hajjar, and R. Reif, "Drastically improved performance in poly-Si TFTs with channel dimensions comparable to grain size," in IEDM Tech. Dig., 1989, pp. 353-356.
5. H. Yin, W. Xianyu, H. Cho, X. Zhang, J. Jung, D. Kim, H. Lim, K. Park, J. Kim, J. Kwon, and T. Noguchi, "Advanced poly-Si TFT with fin-like channels by ELA," IEEE Electron Device Lett., vol. 27, no. 5, pp. 357-359, May 2006.
6. H. Yin, W. Xianyu, A. Tikhonovsky, and Y. S. Park, "Scalable 3-D fin-like poly-Si TFT and Its nonvolatile memory application," IEEE Trans. Electron Devices, vol. 55, no. 2, pp. 578-584, Feb. 2008.
7. C. W. Chang, S. F. Chen, C. L. Chang, C. K. Deng, J. J. Huang, and T. F. Lei, "High-performance nanowire TFTs with metal-induced lateral crystallized poly-Si channels," IEEE Electron Device Lett., vol. 29, no. 5, pp. 474-476, May 2008.
8. Y. C. Wu, T. C. Chan, P. T. Liu, Y. C. Wu, C. W. Chou, C. H. Tu, J. C. Lou, and C. Y. Chang, "Mobility enhancement of polycrystalline-Si thin-film transistors using nanowire channels by pattern-dependent metal-induced lateral crystallization," Appl. Phys. Lett., vol. 87, no. 14, pp. 143 504-143 506, Sep. 2005.
9. C. J. Su, H. C. Lin, H. H. Tsai, H. H. Hsu, T. M. Wang, T. Y. Huang, and W. X. Ni, "Operations of poly-Si nanowire thin-film transistors with a multiple-gated configuration," Nanotechnology, vol. 18, no. 21, pp. 215 205-215 211, May 2007.
10. T. Uchida, "Present and future trend of electron device technology in flat panel display," in IEDM Tech. Dig., 1991, pp. 5-10.
11. C. C. Tsai, Y. J. Lee, J. L. Wang, K. F. Wei, I. C. Lee, C. C. Chen, and H. C. Cheng, "High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallization," Solid State Electron., vol. 52, no. 3, pp. 365-371, Mar. 2008.
12. 3 plasma passivation on electrical characteristics of polysilicon thin-film transistors by pattern-dependent metal-induced lateral crystallization," J. Electrochem. Soc., vol. 152, no. 7, pp. G545-G549, Jun. 2005.
13. 3 plasma passivation on n-channel polycrystalline silicon thin-film transistors," IEEE Trans. Electron Devices, vol. 44, no. 1, pp. 64-68, Jan. 1997.
14. Y. K. Choi, T. J. King, and C. Hu, "Spacer FinFET: Nanoscale double-gate CMOS technology for the terabit era," Solid State Electron., vol. 46, no. 10, pp. 1595-1601, Oct. 2002.
15. J. W. Yang and J. G. Fossum, "On the feasibility of nanoscale triple-gate CMOS transistors," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159-1164, Jun. 2005.
16. J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, C. Cabral, R. Amos, C. Lavoie, R. Roy, J. Newbury, E. Sullivan, J. Benedict, P. Saunders, K. Wong, D. Canaperi, M. Krishnan, K. L. Lee, B. A. Rainey, D. Fried, P. Cottrell, H. S. P. Wong, M. Ieong, and W. Haensch, "Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation," in IEDM Tech. Dig., 2002, pp. 247-250.
17. W. B. Jackson, N. M. Johnson, C. C. Tsai, I.-W. Wu, A. Chiang, and D. Smith, "Hydrogen diffusion in polycrystalline silicon thin films," Appl. Phys. Lett., vol. 61, no. 14, pp. 1670-1672, Oct. 1992.