A hardware architecture for real-time video segmentation utilizing memory reduction techniques

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 19, Issue 2, 2009, Pages 226-236

  Jiang, Hongtu ^a,b   Ardö, Håkan ^a   Öwall, Viktor ^a  

^a LUND UNIVERSITY   (Sweden)

^b ERICSSON RESEARCH   (Sweden)

Author keywords

Field programmable gate array (FPGA); Mixture of Gaussian (MoG); Video segmentation

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; SECURITY SYSTEMS; TRELLIS CODES; VIDEO AMPLIFIERS;

AUTOMATED VIDEO SURVEILLANCES; DATA FLOWS; DEDICATED HARDWARES; FIELD-PROGRAMMABLE GATE ARRAY (FPGA); FRAMES PER SECONDS; HARDWARE ARCHITECTURES; HARDWARE EFFICIENCIES; HARDWARE PLATFORMS; HIGH RESOLUTIONS; LONG-TERM EFFECTS; MEMORY ACCESS; MEMORY BANDWIDTHS; MEMORY REDUCTIONS; MIXTURE OF GAUSSIAN (MOG); PARAMETER SETTINGS; REAL-TIME PERFORMANCE; REAL-TIME SEGMENTATIONS; REAL-TIME TESTBENCH; REAL-TIME VIDEO SEGMENTATIONS; SEGMENTATION ALGORITHMS; SEGMENTATION RESULTS; VIDEO SEGMENTATION; WHOLE SYSTEMS; WORD-LENGTH REDUCTIONS;

IMAGE SEGMENTATION;

EID: 59649113810     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2008.2009244     Document Type: Article

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