Characterization of polymetal gate transistors with low-temperature atomic-layer-deposition-grown oxide spacer

IEEE Electron Device Letters

Volumn 30, Issue 2, 2009, Pages 181-184

  Lee, Ga Won ^a   Lee, Hi Duck ^a   Lim, Kwan Yong ^b   Kim, Yong Soo ^b   Yang, Hong Sun ^b   Cho, Gyu Seog ^b   Park, Sung Kye ^b   Hong, Sung Joo ^b  

^a Chungnam National University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

Atomic layer deposition (ALD); Data retention time; DRAM; Spacer; Tungsten (W) gate

Indexed keywords

ATOMIC PHYSICS; ATOMS; BORON; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC NETWORK ANALYSIS; ELECTRIC PROPERTIES; FABRICATION; HYDROGEN; TRANSISTORS; TUNGSTEN;

ATOMIC LAYER DEPOSITION (ALD); DATA RETENTION TIME; DRAM; SPACER; TUNGSTEN (W) GATE;

ATOMIC LAYER DEPOSITION;

EID: 59649110555     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2010141     Document Type: Article

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