C-CREST technique for combinational logic SET testing

IEEE Transactions on Nuclear Science

Volumn 55, Issue 6, 2008, Pages 3347-3351

  Ahlbin, J R ^a   Black, J D ^b   Massengill, L W ^a   Amusan, O A ^a   Balasubramanian, A ^a   Casey, M C ^a   Black, D A ^b   McCurdy, M W ^b   Reed, R A ^a   Bhuva, B L ^a  

^a VANDERBILT UNIVERSITY   (United States)

^b VANDERBILT UNIVERSITY   (United States)

Author keywords

Combinational logic; DICE latch; Single event; Single event transient; Single event upset; Window of vulnerability

Indexed keywords

ERRORS; TRANSIENTS; WINDOWS;

COMBINATIONAL LOGIC; DICE LATCH; SINGLE EVENT; SINGLE EVENT TRANSIENT; SINGLE EVENT UPSET; WINDOW OF VULNERABILITY;

RADIATION EFFECTS;

EID: 58849139647     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2008.2005900     Document Type: Conference Paper

References (15)

1. R. C. Baumann, "Single event effects in advanced CMOS technology," presented at the IEEE Nuclear Space Radiation Effects Conf. Short Course Text, 2005.
2. J. Benedetto, P. Eaton, K. Avery, D. Mavis, M. Gadlage, T. Turflinger, P. E. Dodd, and G. Vizkelethyd, "Heavy ion induced digital single event transients in deep submicron processes," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3480-3485, Dec. 2004.
3. J. M. Benedetto, P. H. Eaton, D. G. Mavis, M. Gadlage, and T. Turflinger, "Variation of digital SET pulse widths and the implications for single event hardening of advanced CMOS processes," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2114-2119, Dec. 2005.
4. S. Buchner, K. Kang, D. Krening, G. Lannan, and R. Schneiderwind, "Dependence of the SEU window of vulnerability of a logic circuit on magnitude of deposited charge," IEEE Trans. Nucl. Sci., vol. 40, no. 6, pp. 1853-1857, Dec. 1993.
5. P. E. Dodd, M. R. Shaneyfelt, J. A. Felix, and J. R. Schwank, "Transients in high-speed digital logic ICs," IEEE Trans. Nucl. Sci., vol. 51, pp. 3278-3384, Dec. 2004.
6. P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, "Modeling the effect of technology trends on soft error rate of combinational logic," in Proc. Int. Conf. Dependable Syst. Networks, 2002.
7. P. Marshall, M. Carts, S. Currie, R. Reed, B. Randall, K. Fritz, K. Kennedy, M. Berg, R. Krithivasan, C. Siedleck, R. Ladbury, C. Marshall, J. Cressler, N. Guofu, K. LaBel, and B. Gilbert, "Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5 AM SiGe circuit for radiation effects self test (CREST)," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2446-2454, Dec. 2005.
8. E. H. Cannon, D. D. Reinhardt, M. S. Gordon, and P. S. Makowenskyj, "SRAM SER in 90, 130, and 180 nm bulk and SOI technologies," in Proc. Int. Reliability Physics Symp., 2004, pp. 300-304.
9. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2874-2878, Dec. 1996.
10. H. S. Kim, "Low speed digital tester hardware manual," NASA-GSFC, 2005.
11. R. A. Reed, M. A. Carts, P. W. Marshall, C. J. Marshall, S. Buchner, M. La. Macchia, B. Mathes, and D. McMorrow, "Single event upset cross sections at various data rates," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2862-2867, Dec. 1996.
12. P. W. Marshall, C. J. Dale, T. R.Weatherford, M. La. Macchia, and K. A. LaBel, "Particle-induced mitigation of SEU sensitivity in high data rate GaAs HIGFET technologies," IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1844-1849, Dec. 1995.
13. S. P. Buchner and M. P. Baze, "Single-event transients in fast electronic circuits," IEEE NSREC Short Course, pp. V-1-V-105, 2001.
14. S. Buchner, M. Baze, D. Brown, D. McMorrow, and J. Melinger, "Comparison of error rates in combinational and sequential logic," IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2209-2216, Dec. 1997.
15. M. J. Gadlage, P. H. Eaton, J. M. Benedetto, M. Carts, V. Zhu, and T. L. Turflinger, "Digital device error rate trends in advanced CMOS technologies," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3466-3471, Dec. 2006.