Transient fault recovery on chip multiprocessor based on dual core redundancy and context saving

Proceedings of the 9th International Conference for Young Computer Scientists, ICYCS 2008

Volumn , Issue , 2008, Pages 148-153

  Gong, Rui ^a   Dai, Kui ^a   Wang, Zhiying ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

Author keywords

Chip multiprocessor; Context saving; Dual core redundancy; Transient fault recovery

Indexed keywords

BANDWIDTH; FAILURE ANALYSIS; FAULT TREE ANALYSIS; FLUORESCENT SCREENS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE; RECOVERY; REDUNDANCY; SYSTEMS ANALYSIS; TELECOMMUNICATION SYSTEMS; TELEVISION PICTURE TUBES;

AND RECOVERIES; CACHE MISSES; CHIP MULTIPROCESSOR; COMMUNICATION BANDWIDTHS; CONTEXT SAVING; DUAL CORE REDUNDANCY; FAULT RECOVERIES; MICRO-PROCESSORS; MULTI-PROCESSORS; NEW APPROACHES; ON CHIPS; TRANSIENT FAULT RECOVERY;

RELIABILITY;

EID: 58349113422     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICYCS.2008.271     Document Type: Conference Paper

References (10)

1. P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi, "Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic," Proc. Intl. Conference on Dependable Systems Networks (DSN'02), pp. 389-398, 2002.
2. S.S. Mukherjee, M. Kontz, and S.K. Reinhardt, "Detailed Design and Evaluation of Redundant Multithreading Alternatives," Proc. 29th Annual Intl. Symp. on Computer Architecture (ISCA '02), pp. 99-110, 2002.
3. M. Gomaa, C. Scarbrough, T.N. Vijaykumar, and I. Pomeranz, "Transient-Fault Recovery for Chip Multiprocessors," Proc. 30th Annual Intl. Symp. on Computer Architecture (ISCA '03), pp. 98-109, 2003.
4. E. Rotenberg, "AR-SMT: A microarchitectural Approach to Fault Tolerance in Microprocessors," Proc. Intl. Symp. on Fault-Tolerant Computing (FTCS'99), pp. 84-91, 1999.
5. S.K. Reinhardt and S.S. Mukherjee, "Transient Fault Detection via Simultaneous Multithreading," Proc. 27th Annual Intl. Symp. on Computer Architecture (ISCA '00), pp. 25-36, 2000.
6. T. Vijaykumar, I. Pomeranz, and K. Cheng, "Transient-Fault Recovery via Simultaneous Multithreading," Proc. 29th Annual Intl. Symp. on Computer Architecture (ISCA '02), pp. 87-98, 2002.
7. C. LaFrieda, E. Ipek, J.F. Martinez, and R. Manohar, "Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor," Proc. Intl. Conference on Dependable Systems Networks (DSN'07), pp. 317-326, 2007.
8. J.C. Smolens, B.T. Gold, B. Falsafi, and J.C. Hoe, "Reunion: Complexity-Effective Multicore Redundancy," Proc. 39th Annual IEEE/ACM Intl. Symp.on Microarchitecture (Micro '06), pp. 223-234, 2006.
9. J.C. Smolens, B.T. Gold, J. Kim, B. Falsafi, J.C. Hoe and A.G. Nowatzyk, "Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth," IEEE Micro, vol.24, no. 6, pp. 22-29, 2004
10. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos, SESC simulator, 2005. http://sesc.sourceforge.net.