Transactional WaveCache: Towards speculative and out-of-order dataflow execution of memory operations

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn , Issue , 2008, Pages 183-190

  Marzulo, Leandro A J ^a   França, Felipe M G ^a   Costa, Vítor Santos ^b  

^a FEDERAL UNIVERSITY OF RIO DE JANEIRO   (Brazil)

^b UNIVERSITY OF PORTO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; DATA STORAGE EQUIPMENT; DATA STRUCTURES; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; INFORMATION THEORY;

ATOMIC REGIONS; FUNCTION CALLS; IMPERATIVE LANGUAGES; MEMORY CONCURRENCIES; MEMORY DISAMBIGUATIONS; MEMORY OPERATIONS; NESTED TRANSACTIONS; SPEC 2000; SPEED-UP; SPEED-UPS; WAVESCALAR;

COMPUTER ARCHITECTURE;

EID: 58049161991     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBAC-PAD.2008.29     Document Type: Conference Paper

References (20)

1. A.-R. Adl-Tabatabai, B. T. Lewis, V. Menon, B. R. Murphy, B. Saha, and T. Shpeisman. Compiler and runtime support for efficient software transactional memory. In Proceedings of the 2006 Conference on Programming language design and implementation, pages 26-37. Jun 2006.
2. C. S. Ananian, K. Asanovic, B. C. Kuszmaul, C. E. Leiserson, and S. Lie. Unbounded transactional memory. IEEE Micro, 26(1):59-69, 2006.
3. J. Chung, C. C. Minh, A. McDonald, T. Skare, H. Chafi, B. D. Carlstrom, C. Kozyrakis, and K. Olukotun. Tradeoffs in transactional memory virtualization. In ASPLOS-XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems, pages 371-381, New York, NY, USA, 2006. ACM.
4. P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid transactional memory. In ASPLOS-XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems, pages 336-346, New York, NY, USA, 2006. ACM.
5. R. Desikan, D. C. Burger, S.W. Keckler, and T. Austin. Sim-alpha: A validated, execution-driven alpha 21264 simulator. Technical Report TR-01-23, UT-Austin Computer Sciences, 2001.
6. V. G. Grafe, G. S. Davidson, J. E. Hoch, and V. P. Holmes. The epsilon dataflow processor. In ISCA '89: Proceedings of the 16th annual international symposium on Computer architecture, pages 36-45, New York, NY, USA, 1989. ACM Press.
7. J. R. Gurd, C. C. Kirkham, and I. Watson. The manchester prototype dataflow computer. Commun. ACM, 28(1):34-52, 1985.
8. M. Herlihy, V. Luchangco, M. Moir, and I. William N. Scherer. Software transactional memory for dynamic-sized data structures. pages 92-101, Jul 2003.
9. M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In ISCA, pages 289-300, 1993.
10. S. Kumar, M. Chu, C. J. Hughes, P. Kundu, and A. Nguyen. Hybrid transactional memory. In Proceedings of Symposium on Principles and Practice of Parallel Programming, Mar 2006.
11. A. McDonald, J. Chung, B. D. Carlstrom, C. C. Minh, H. Chafi, C. Kozyrakis, and K. Olukotun. Architectural semantics for practical transactional memory. In ISCA '06: Proceedings of the 33rd annual international symposium on Computer Architecture, pages 53-65, Washington, DC, USA, 2006. IEEE Computer Society.
12. J. E. B. Moss. Open nested transactions: Semantics and support. In WMPI, Austin, TX, February 2006.
13. G. M. Papadopoulos and D. E. Culler. Monsoon: an explicit token-store architecture. In ISCA '90: Proceedings of the 17th annual international symposium on Computer Architecture, pages 82-91, New York, NY, USA, 1990. ACM Press.
14. K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. W. Keckler, and C. R. Moore. Exploiting ilp, tlp, and dlp with the polymorphous trips architecture. SIGARCH Comput. Archit. News, 31(2):422-433, 2003.
15. N. Shavit and D. Touitou. Software transactional memory. In PODC '95: Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing, pages 204-213, New York, NY, USA, 1995. ACM.
16. S. Swanson. The WaveScalar Architecture. PhD thesis, University of Washington, 2006.
17. S. Swanson, K. Michelson, A. Schwerin, and M. Oskin. Wavescalar. In Microarchitecture, 2003. MICRO-36. Proceedings. 36th Annual IEEE/ACM International Symposium on, pages 291-302, 2003.
18. S. Swanson, A. Schwerin, M. Mercaldi, A. Petersen, A. Putnam, K. Michelson, M. Osin, and S. Eggers. The wavescalar architecture. ACM Transactions on Computer Systems, TOCS, 25 February 2007.
19. R. M. Tomasulo. An efficient algorithm for exploring multiple arithmetic units. IBM Journal of Research and Development, 11:25-33, Jan 1967.
20. E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. Baring it all to software: Raw machines. Computer, 30(9):86-93, Sept. 1997.