VHDL implmentation of a BCH minimum weight decoder for double error

National Radio Science Conference, NRSC, Proceedings

Volumn 2, Issue , 2001, Pages 361-366

  El Medany, W M ^a   Harrison, C G ^b   Garrell, P G ^c   Hardy, C J ^b  

^a MENOUFIA UNIVERSITY   (Egypt)

^b UNIVERSITY OF MANCHESTER   (United Kingdom)

^c LANCASTER UNIVERSITY   (United Kingdom)

Author keywords

Block codes; Error correction; Error correction codes; Field programmable gate arrays; Hamming weight; Hardware design languages; Maximum likelihood decoding; Test pattern generators; Testing; Writing

Indexed keywords

ALGORITHMS; BLOCK CODES; CODES (SYMBOLS); COMPUTATIONAL LINGUISTICS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DECODING; ERROR CORRECTION; ERRORS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; LOGIC GATES; MAXIMUM LIKELIHOOD; SIGNAL RECEIVERS; TECHNICAL WRITING; TESTING;

ERROR CORRECTION CODES; HAMMING WEIGHTS; HARDWARE DESIGN LANGUAGE; MAXIMUM LIKELIHOOD DECODING; TEST PATTERN GENERATOR;

C (PROGRAMMING LANGUAGE);

EID: 22944458735     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NRSC.2001.929391     Document Type: Conference Paper

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