A network-flow approach to timing-driven incremental placement for ASICs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 375-382

  Dutt, Shantanu ^a   Ren, Huan ^a   Yuan, Fenghua ^a   Suthar, Vishal ^a  

^a UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK SUITES; COMPUTER-AIDED DESIGN; CRITICAL PATH DELAYS; DELAY FUNCTIONS; INCREMENTAL PLACEMENT; INTERNATIONAL CONFERENCES; NETWORK FLOWS; PERFORMANCE IMPROVEMENTS; QUADRATIC OBJECTIVE FUNCTIONS; RUN TIME; RUN TIMES; STANDARD CELLS; TIMING DRIVEN; WHITE SPACE; WIRE LENGTHS;

ADDERS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; PLACERS; STANDARDS; TIME MEASUREMENT;

INTEGRATED CIRCUIT TESTING;

EID: 46149124374     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320061     Document Type: Conference Paper

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