A highly scalable capacitorless double gate quantum well single transistor DRAM: 1T-QW DRAM

IEEE Electron Device Letters

Volumn 29, Issue 12, 2008, Pages 1405-1407

  Ertosun, M Günhan ^a   Kapur, Pawan ^a   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

Author keywords

Double gate (DG) MOSFETs; DRAM; Floating body DRAM; Fully depleted; Scaled CMOS

Indexed keywords

DATA STORAGE EQUIPMENT; DRAIN CURRENT; MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR QUANTUM WELLS; SEMICONDUCTOR QUANTUM WIRES;

DOUBLE-GATE (DG) MOSFETS; DRAM; FLOATING-BODY DRAM; FULLY DEPLETED; SCALED CMOS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 57049116511     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2007508     Document Type: Article

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