A variable-phase ring oscillator and PLL architecture for integrated phased array transceivers

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 11, 2008, Pages 2446-2463

  Krishnaswamy, Harish ^a   Hashemi, Hossein ^a  

^a University of Southern California   (United States)

Author keywords

Phase locked loops (PLLs); Phase noise; Phase shifters; Phased arrays; Sensitivity; Transceivers

Indexed keywords

ARRAY TRANSCEIVERS; CMOS PROCESSES; KEY BUILDING BLOCKS; LOW POWERS; MEASURED RESULTS; PERFORMANCE METRICS; PHASED ARRAYS; PLL ARCHITECTURES; RECEIVE MODES; RING OSCILLATORS; SENSITIVITY;

PHASE LOCKED LOOPS; PHASE SHIFT; PHASE SHIFTERS; TRANSCEIVERS;

ARCHITECTURAL DESIGN;

EID: 56849132144     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2005445     Document Type: Article

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