Effect of process mismatches on integrated CMOS phased arrays based on multiphase tuned ring oscillators

IEEE Transactions on Microwave Theory and Techniques

Volumn 56, Issue 6, 2008, Pages 1305-1315

  Krishnaswamy, Harish ^a,b   Hashemi, Hossein ^a,b  

^a IEEE

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

CMOSFET oscillators; Error analysis; Oscillators; Phased arrays; Quadrature amplitude modulation (QAM)

Indexed keywords

COMPUTER GENERATED HOLOGRAPHY; COMPUTER NETWORKS; NETWORKS (CIRCUITS); NEURAL NETWORKS; OSCILLATORS (ELECTRONIC); TIMING CIRCUITS; TRANSCEIVERS;

(E ,3E) PROCESS; ARRAY PERFORMANCE; CLOCK AND DATA RECOVERY CIRCUITS (CDRC); CMOS PROCESSING; COUPLED-OSCILLATOR ARRAYS; FOUR-CHANNEL; LOW POWERS; MISMATCH CALIBRATION; MULTI-PHASE; PHASE PROGRESSIONS; PHASED ARRAYS; RING OSCILLATORS; SINGLE CHIPS; TRANSCEIVER ARCHITECTURE;

CMOS INTEGRATED CIRCUITS;

EID: 45249086586     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2008.923344     Document Type: Article

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