-
3
-
-
33744484309
-
Biobench: A benchmark suite of bioinformatics applications
-
Mar
-
K. Albayraktaroglu, A. Jaleel, X. Wu, M. Franklin, B. Jacob, C.-W. Tseng, and D. Yeung. Biobench: A benchmark suite of bioinformatics applications. In Procs. of ISPASS 2005. Mar 2005.
-
(2005)
Procs. of ISPASS 2005
-
-
Albayraktaroglu, K.1
Jaleel, A.2
Wu, X.3
Franklin, M.4
Jacob, B.5
Tseng, C.-W.6
Yeung, D.7
-
4
-
-
35348875372
-
Performance pathologies in hardware transactional memory
-
ACM
-
J. Bobba, K. E. Moore, H. Volos, L. Yen, M. D. Hill, M. M. Swift, and D. A. Wood. Performance pathologies in hardware transactional memory. ISCA, pages 81-91. ACM, 2007.
-
(2007)
ISCA
, pp. 81-91
-
-
Bobba, J.1
Moore, K.E.2
Volos, H.3
Yen, L.4
Hill, M.D.5
Swift, M.M.6
Wood, D.A.7
-
5
-
-
0034268943
-
A portable programming interface for performance evaluation on modern processors
-
Fall
-
S. Browne, J. Dongarra, N. Garner, G. Ho, and P. Mucci. A portable programming interface for performance evaluation on modern processors. The International Journal of High Performance Computing Applications, 14(3):189-204, Fall 2000.
-
(2000)
The International Journal of High Performance Computing Applications
, vol.14
, Issue.3
, pp. 189-204
-
-
Browne, S.1
Dongarra, J.2
Garner, N.3
Ho, G.4
Mucci, P.5
-
6
-
-
35348853739
-
An effective hybrid transactional memory system with strong isolation guarantees
-
Jun
-
C. Cao Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An effective hybrid transactional memory system with strong isolation guarantees. In Procs. of the 3th ISCA. Jun 2007.
-
(2007)
Procs. of the 3th ISCA
-
-
Cao Minh, C.1
Trautmann, M.2
Chung, J.3
McDonald, A.4
Bronson, N.5
Casper, J.6
Kozyrakis, C.7
Olukotun, K.8
-
7
-
-
33748847902
-
The common case transactional behavior of multithreaded programs
-
Feb
-
J. Chung, H. Chafi, C. Cao Minh, A. McDonald, B. D. Carlstrom, C. Kozyrakis, and K. Olukotun. The common case transactional behavior of multithreaded programs. In 12th HPCA. Feb 2006.
-
(2006)
12th HPCA
-
-
Chung, J.1
Chafi, H.2
Cao Minh, C.3
McDonald, A.4
Carlstrom, B.D.5
Kozyrakis, C.6
Olukotun, K.7
-
8
-
-
34547403150
-
Hybrid transactional memory
-
P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid transactional memory. In Procs. of the 12th ASPLOS. pages 336-346, 2006.
-
(2006)
Procs. of the 12th ASPLOS
, pp. 336-346
-
-
Damron, P.1
Fedorova, A.2
Lev, Y.3
Luchangco, V.4
Moir, M.5
Nussbaum, D.6
-
10
-
-
56749162554
-
Parallelizing union-find in constraint handling rules using confluence
-
Oct
-
T. Fruhwirth. Parallelizing union-find in constraint handling rules using confluence. In 21st Conference on Logic Programming ICLP. Oct 2005.
-
(2005)
21st Conference on Logic Programming ICLP
-
-
Fruhwirth, T.1
-
11
-
-
34548036715
-
STMBench7: A benchmark for software transactional memory
-
ACM, Mar
-
R. Guerraoui, M. Kapalka, and J. Vitek. STMBench7: A benchmark for software transactional memory. In Procs. of EuroSys2007, 315-324. ACM, Mar 2007.
-
(2007)
Procs. of EuroSys2007
, pp. 315-324
-
-
Guerraoui, R.1
Kapalka, M.2
Vitek, J.3
-
12
-
-
31844442209
-
Composable memory transactions
-
Chicago, Illinois, June
-
T. Harris, S. Marlow, S. P. Jones, and M. Herlihy. Composable memory transactions. In PPoPP'05, Chicago, Illinois, June 2005.
-
(2005)
PPoPP'05
-
-
Harris, T.1
Marlow, S.2
Jones, S.P.3
Herlihy, M.4
-
13
-
-
0027262011
-
Transactional memory: Architectural support for lock-free data structures
-
M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In Procs. of the Twentieth Annual ISCA, 1993.
-
(1993)
Procs. of the Twentieth Annual ISCA
-
-
Herlihy, M.1
Moss, J.E.B.2
-
15
-
-
56749137026
-
A concurrent constraint handling rules implementation in haskell with software transactional memory
-
Jan
-
E. S. L. Lam and M. Sulzmann. A concurrent constraint handling rules implementation in haskell with software transactional memory. In DAMP'07. Jan 2007.
-
(2007)
DAMP'07
-
-
Lam, E.S.L.1
Sulzmann, M.2
-
16
-
-
56749110573
-
-
J. R. Larus and R. Rajwar. Transactional Memory. Morgan and Claypool, 2006.
-
J. R. Larus and R. Rajwar. Transactional Memory. Morgan and Claypool, 2006.
-
-
-
-
18
-
-
20344403770
-
Montecito: A dual-core, dual-thread itanium processor
-
C. McNairy and R. Bhatia. Montecito: A dual-core, dual-thread itanium processor. IEEE Micro, 25(2): 10-20, 2005.
-
(2005)
IEEE Micro
, vol.25
, Issue.2
, pp. 10-20
-
-
McNairy, C.1
Bhatia, R.2
-
19
-
-
47349098275
-
Minebench: A benchmark suite for data mining workloads
-
IEEE
-
R. Narayanan, B. Özisikyilmaz, J. Zambreno, G. Memik, and A. N. Choudhary. Minebench: A benchmark suite for data mining workloads. In IISWC, pages 182-188. IEEE, 2006.
-
(2006)
IISWC
, pp. 182-188
-
-
Narayanan, R.1
Özisikyilmaz, B.2
Zambreno, J.3
Memik, G.4
Choudhary, A.N.5
-
21
-
-
0004763160
-
The nofib benchmark suite of haskell programs
-
Springer Verlag
-
W. Partain. The nofib benchmark suite of haskell programs. In Workshops in Computing, Springer Verlag. 1993.
-
(1993)
Workshops in Computing
-
-
Partain, W.1
-
25
-
-
79960139544
-
Unreadtvar: Extending haskell software transactional memory for performance
-
Apr
-
N. Sonmez, C. Perfumo, S. Stipic, A. Cristal, O. Unsal., and M. Valero. Unreadtvar: Extending haskell software transactional memory for performance. In TFP 2007. Apr 2007.
-
(2007)
TFP 2007
-
-
Sonmez, N.1
Perfumo, C.2
Stipic, S.3
Cristal, A.4
Unsal, O.5
Valero, M.6
|