An efficient method for large-scale gate sizing

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 9, 2008, Pages 2760-2773

  Joshi, Siddhart ^a   Boyd, Stephen ^a  

^a Stanford University   (United States)

Author keywords

Gate sizing; Geometric programming (GP); Large scale optimization

Indexed keywords

GATES (TRANSISTOR); ITERATIVE METHODS; MATHEMATICAL PROGRAMMING; NUMERICAL METHODS; TIMING CIRCUITS;

COMBINATIONAL LOGIC CIRCUITS; GATE SIZING; GEOMETRIC PROGRAM; GEOMETRIC PROGRAMMING; INTERIOR-POINT METHOD; LARGE-SCALE OPTIMIZATION; NUMERICAL EXPERIMENTS; TIMING CONSTRAINTS;

COMPUTER CIRCUITS;

EID: 56349166783     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.920087     Document Type: Article

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