Delay and area optimization for discrete gate sizes under double-sided timing constraints

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1993, Pages

  Chuang, Weitong ^a   Sapatnekar, Sachin S ^a   Hajj, Ibrahim N ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; LINEAR PROGRAMMING; OPTIMIZATION;

DELAY/AREA OPTIMIZATION; DISCRETE GATE SIZES; DOUBLE-SIDED TIMING CONSTRAINTS; THREE-STEP ALGORITHM;

GATES (TRANSISTOR);

EID: 0027271133     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)