A DLL-based variable-phase clock buffer

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 12, 2007, Pages 1072-1076

  Chen, Chao Chyun ^a   Chang, Jung Yu ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Clock; Delay locked loop (DLL); Variable phase

Indexed keywords

CLOCKS;

CLOCK BUFFER; CMOS PROCESSS; DELAY-LOCKED LOOPS; MULTIPHASE-OUTPUT; OUTPUT PHASE; ROOT MEAN SQUARED; VARIABLE PHASE; VOLTAGE-CONTROLLED DELAY LINES;

DELAY LOCK LOOPS;

EID: 56349108183     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.906172     Document Type: Article

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