256-Mb double-data-rate SDRAM with a 10-mW analog DLL circuit

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2000, Pages 74-75

  Yahata, Hideharu ^a   Okuda, Yuichi ^a   Miyashita, Hiroki ^a   Chigasaki, Hideo ^a   Taruishi, Binhaku ^a   Akiba, Takesada ^a   Kawase, Yasushi ^a   Tachibana, Toshikazu ^a   Ueda, Shigeki ^a   Aoyama, Satoshi ^a   Tsukimori, Akifumi ^a   Shibata, Ken ^a   Horiguchi, Masashi ^a   Saiki, Yozo ^a   Nakagome, Yoshinobu ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; LINEAR INTEGRATED CIRCUITS; TIMING CIRCUITS;

ANALOG DELAYED LOCKED LOOP (DLL) CIRCUITS; DOUBLE DATA RATE STATIC DYNAMIC RANDOM ACCESS MEMORY (DDR SDRAM);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0033683624     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)