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Volumn , Issue , 2008, Pages 388-389

Compact model of a dual gate CNTFET: Description and circuit application

Author keywords

[No Author keywords available]

Indexed keywords

DRAIN CURRENT; GALERKIN METHODS; LOGIC CIRCUITS; NANOTECHNOLOGY; NETWORKS (CIRCUITS); POWDERS; PREDICTIVE CONTROL SYSTEMS; SCHOTTKY BARRIER DIODES; SWITCHING CIRCUITS; SWITCHING THEORY;

EID: 55349098254     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANO.2008.120     Document Type: Conference Paper
Times cited : (6)

References (5)
  • 1
    • 15844407150 scopus 로고    scopus 로고
    • Benchmarking nanotechnology for high-performance and low-power logic transistor applications
    • March
    • R. Chau et al., "Benchmarking nanotechnology for high-performance and low-power logic transistor applications," IEEE Trans. On Nanotech., vol. 4, N° 2, pp. 153-158, March 2005.
    • (2005) IEEE Trans. On Nanotech , vol.4 , Issue.2 , pp. 153-158
    • Chau, R.1
  • 2
    • 33750597000 scopus 로고    scopus 로고
    • Carbon nanotube field-effect transistors for high-performance digital circuits-DC analysis and modeling toward optimum transistor structure
    • Nov
    • A. Raychowdhury et al., "Carbon nanotube field-effect transistors for high-performance digital circuits-DC analysis and modeling toward optimum transistor structure," IEEE TED, vol. 53, N° 11, pp. 2711-2717, Nov. 2006.
    • (2006) IEEE TED , vol.53 , Issue.11 , pp. 2711-2717
    • Raychowdhury, A.1
  • 3
    • 26644474574 scopus 로고    scopus 로고
    • High performance carbon nanotube field-effect transistor with tunable polarities
    • Sept
    • Y.-M. Lin et al., "High performance carbon nanotube field-effect transistor with tunable polarities," IEEE Trans. On Nanotech., vol. 4, N° 5, pp. 481-489, Sept. 2005.
    • (2005) IEEE Trans. On Nanotech , vol.4 , Issue.5 , pp. 481-489
    • Lin, Y.-M.1
  • 4
    • 49049102424 scopus 로고    scopus 로고
    • CNTFET Modeling and Reconfigurable Logic Circuit Design
    • Nov
    • I. O'connor et al., "CNTFET Modeling and Reconfigurable Logic Circuit Design," IEEE TCAS, vol. 54, N° 11, Nov. 2007.
    • (2007) IEEE TCAS , vol.54 , Issue.11
    • O'connor, I.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.