Stochastic decoding of linear block codes with high-density parity-check matrices

IEEE Transactions on Signal Processing

Volumn 56, Issue 11, 2008, Pages 5733-5739

  Sharifi Tehrani, Saeed ^a   Jego, Christophe ^b   Zhu, Bo ^c   Gross, Warren J ^a  

^a MCGILL UNIVERSITY   (Canada)

^b LAB STICC   (France)

^c NORTEL NETWORKS   (Canada)

Author keywords

BCH codes; Block turbo codes; Reed Solomon codes; Soft input soft output decoding; Stochastic decoding

Indexed keywords

BLOCK CODES; CODES (SYMBOLS); DECODING; QUADRATURE PHASE SHIFT KEYING; REED-SOLOMON CODES; STOCHASTIC PROGRAMMING; TURBO CODES;

BCH CODES; BLOCK TURBO CODES; DECODING PERFORMANCES; FLOATING-POINT; HARDWARE COMPLEXITIES; HIGH-DENSITY; LINEAR BLOCK CODES; LOWER COMPLEXITIES; SISO DECODING; SOFT-INPUT SOFT-OUTPUT DECODING; STOCHASTIC; STOCHASTIC DECODING;

ITERATIVE DECODING;

EID: 54949142190     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2008.929337     Document Type: Article

References (20)

1. C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon limit error correcting coding and decoding: Turbo codes," in IEEE Int. Conf. Commun., May 19993, pp. 1064-1070.
2. F. Kschischang, B. Frey, and H. Loeliger, "Factor graphs and the sum-product algorithim," IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 498-519, Feb. 2001.
3. B. Gaines, Advances in information Systems Science. New York: Plenum, 1969, ch. 2, pp. 37-172.
4. V. Gaudet and A Rapley, "Iterative decoding using stochastic computation," Electron. Lett., vol. 39, no. 3, pp. 299-301, Feb. 2003.
5. A. Rapley, C. Winstead, V. Gaudet, and C. Schlegel, "Stochastic iterative decoding on factor graphs," in Proc. 3rd Int. Symp. Turbo Codes Related Topics, Brest, France, Sep. 2003, pp. 507-510.
6. W. J. Gross, V. Gaudet, and A. Milner, "Stochastic implementation of LDFC decoders," in Conf. Rec. 39th Asilomar Conf. Signals, Syst., Computers, Pacific Grove, CA, Nov. 2005, pp. 713-717.
7. C. Winstead, V. Gaudet, A. Rapley, and C. Schlegel, "Stochastic iterative decoders," in Proc. IEEE Int. Symp. Inf. Theor. (ISIT , Adelaide, SA, Sep. 2005, pp. 1116-1120.
8. C. Winstead, "Error-control decoders and probabilistic computation," in Tohoku Univ. 3rd SOIM-COE Conf., Sendai, Japan, Oct. pp. 349-352, Invited Paper.
9. S. Sharifi Tehrani, W. J. Gross, and S. Mannor, "Stochastic decoding of LDPC codes," IEEE Commun. Lett., vol. 10, no. 10, pp. 716-718, Oct. 2006.
10. S. Sharifi Tehrani, S. Mannor, and W. J. Gross, "An area-efficient FPGA-based architecture for fully-parallel stochastic LDPC decoding," in Proc. IEEE Workshop Signal Process. Syst., Shanghai, China, Oct. 2007, pp. 255-260.
11. S. Sharifi Tehrani, S. Mannor, and W. J. Gross, "Fully parallel stochastic LDPC decoders," IEEE Trans. Signal Process., vol. 56, no. 11, pp. 5692-5703, Nov. 2008.
12. J. Jiang and K. R. Narayanan, " Iterative soft-input soft-output decoding of Reed-Solomon codes by adapting the parity-check matrix," IEEE Trans. Inf. Theory, vol. 52, no. 8, pp. 3746-3756, Aug. 2006.
13. C. Jego and W. J. Gross, "Turbo decoding of product codes based on the modified adaptive belief propagation algorithm," in Proc. IEEE Int. Symp. Inf. Theory, Nice, Jun. 2007, pp. 641-645.
14. R. Pyndiah, "Near-optimum decoding of product code: Block turbo codes," IEEE Trans. Commun., vol. 46, no. 88, pp. 1003-1010, Aug. 1998.
15. S. Sharifi Tehrani, S. Mannor, and W. J. Gross, "Survey of stochastic computation on factor graphs," in Proc. 37th Int. Symp. Multiple-Valued Logic (ISMVL), Oslo, Norway, May 2007, pp. 54-59.
16. M. R. Yazdam, S. Hemati, and A. Banihashemi, "Improving belief propagation on graphs with cycles," IEEE Commun. Lett., vol. 8, no. 1, pp. 57-59, Jan. 2004.
17. J. Chen and M. Fossorier, "Density evolution for two improved BP-based decoding algorithms of LDPC codes," IEEE Commun. Lett., vol. 6, no. 5, pp. 208-210, May 2002.
18. F. Chiaraluce and R. Garello, "Extended Hamming product codes analytical performance evaluation for low error rate applications," IEEE Trans. Wireless Commun., vol. 3, no. 6, pp. 2353-2361, Nov. 2004.
19. K. K. Gunnam, G. S. Choi, and M. B. Yeary, "A parallel VLSI architecture for layered decoding for array LDPC codes," in Proc. 20th Int. Conf. VLSI Design, Washington, DC, Jan. 2007, pp. 738-743.
20. A. Blanksby and C. Howland, "A 690-mw 1-gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE J. Solid-State Circuits vol. 37, no. 3, pp. 404-412, Mar. 2002.