An area-efficient FPGA-based architecture for fully-parallel stochastic LDPC decoding

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2007, Pages 255-260

  Tehrani, Saeed Sharifi ^a   Mannor, Shie ^a   Gross, Warren J ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

Iterative decoding; Low density parity check (LDPC) codes; Stochastic decoding

Indexed keywords

ARTIFICIAL INTELLIGENCE; BIT ERROR RATE; DECODING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INFORMATION THEORY; PARALLEL ALGORITHMS; SIGNAL PROCESSING; TECHNICAL PRESENTATIONS; TRANSCEIVERS;

ALTERNATIVE METHODS; AREA REQUIREMENTS; BIT ERRORS; CORRECTING CODES; FACTOR GRAPHS; HARDWARE ARCHITECTURES; LDPC CODES; LDPC DECODERS; LDPC DECODING; LOW COMPLEXITIES; LOW-DENSITY PARITY-CHECK (LDPC) CODES; LOW-DENSITY PARITY-CHECK CODES; PARALLEL DECODING; PERFORMANCE LOSSES; PROPOSED ARCHITECTURES; STOCHASTIC DECODING; SUM-PRODUCT ALGORITHMS; XILINX VIRTEX;

ITERATIVE DECODING;

EID: 47949120496     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2007.4387554     Document Type: Conference Paper

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