Stochastic implementation of LDPC decoders

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn 2005, Issue , 2005, Pages 713-717

  Gross, Warren J ^a   Gaudet, Vincent C ^b   Milner, Aaron ^b  

^a MCGILL UNIVERSITY   (Canada)

^b UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); STANDARDS; STOCHASTIC PROGRAMMING; THROUGHPUT;

BINARY STREAMS; COMMUNICATIONS STANDARDS; ITERATIVE DECODING ARCHITECTURES; STOCHASTIC DECODERS;

ITERATIVE DECODING;

EID: 33847682327     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

1. R. G. Gallager, "Low-density parity-check codes," IRE Transactions on Information Theory, vol. 8, pp. 21-28, January 1962.
2. F. Lustenberger, M. Helfenstein, H. A. Loeliger, F. Tarkoy, and G. S. Moschytz, "All-analog decoder for a binary (18,9,5) trellis code," in Proceedings of the 1999 European Solid-state Circuits Conference (ESSIRC '99), September 1999, pp. 362-265.
3. M. Moerz, T. Gabara, R. Yan, and J. Hagenauer, "An analog 0.25μm BiCMOS tailbiting MAP decoder," in IEEE International Solid-State Circuits Conference Digest of Technical Papers, February 2000, pp. 356-357.
4. C. Winstead, J. Dai, S. Little, C. Myers, C. Schlegel, Y.-B. Kim, and W. J. Kim, "Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS," in IEEE International Symposium on Information Theory, June 2001, p. 330.
5. C. Winstead, N. Nguyen, V. Gaudet, and C. Schlegel, "Low-voltage CMOS circuits for analog iterative decoders," accepted for publication in IEEE Transactions on Circuits and Systems I: Regular Papers.
6. S. Hemati, A. H. Banihashemi, and C. Plett, "A high-speed analog min-sum iterative decoder," in Proceedings of the IEEE International Symposium on Information Theory (ISIT 2005), September 2005, pp. 1768-1772.
7. D. Vogrig, A. Gerosa, A. Neviani, A. G. Amat, G. Montorsi, and S. Benedetto, "A 0.35-μm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code," IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 753-762, March 2005.
8. M. Arzel, C. Lahuec, F. Seguin, D. Gnaedig, and M. Jezequel, "Analoc slice turbo decoding," in Proceedings of the IEEE International Symposium on Circuits and Systems, May 2005, pp. 332-335.
9. V. C. Gaudet and A. C. Rapley, "Iterative decoding using stochastic computation," Electronics Letters, vol. 39, no. 3, pp. 299-301, January 6 2003.
10. B. R. Gaines, "Stochastic computing systems," in Advances in Information Systems Science, J. T. Tou, Ed. Plenum Press, 1969, ch. 2, pp. 37-172.
11. B. D. Brown and H. C. Card, "Stochastic neural computation I: Computational elements," IEEE Transactions on Computers, vol. 50, no. 9, pp. 891-905, September 2001.
12. C. Berrou, A. Glavieux, and P. Thitimajsjima, "Near Shannon limit error-correcting coding and decoding: Turbo codes," in Proceedings of the IEEE International Conference on Communications, vol. 2, May 23-26 1993, pp. 1064-1070.
13. F. R. Kschischang, B. J. Frey, and H.-A. Loeliger, "Factor graphs and the sum-product algorithm," IEEE Transactions on Information Theory, vol. 47, no. 2, pp. 498-519, February 2001.
14. J. Pearl, Probabilistic Reasoning in Intelligent Systems: Networks of Plausible Inference. Morgan Kaufmann, 1988.
15. C. Winstead, A. Rapley, V. Gaudet, and C. Schlegel, "Stochastic iterative decoders," in IEEE International Symposium on Information Theory, September 2005, pp. 1116-1120.
16. A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404-412, March 2002.
17. K. Cattell and J. C. Muzio, "Synthesis of one-dimensional linear hybrid cellular automata," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 3, pp. 325-335, March 1996.