A 90nm 512Mb 166MHz multilevel cell flash memory with 1.5MByte/s programming

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Taub, Mase ^a   Bains, Rupinder ^a   Barkley, Gerald ^a   Castro, Hernan ^a   Christensen, Gregory ^a   Eilert, Sean ^a   Fackenthal, Rich ^a   Giduturi, Hari ^a   Goldman, Matthew ^a   Haid, Chris ^a   Hague, Rezaul ^a   Parat, Krishna ^a   Peterson, Steve ^a   Proescholdt, Andrew ^a   Ramamurthi, Karthi ^a   Ruby, Paul ^a   Sivakumar, Balaji ^a   Smidt, Alec ^a   Srinivasan, Balaji ^a   Szwarc, Martin ^a   Tedrow, Kerry ^a   Young, Doug ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTI-LEVEL CELL FLASH MEMORY; OPTIMIZED PROGRAM CONTROL HARDWARE; SYNCHRONOUS OPERATION;

COMPUTER HARDWARE; COMPUTER PROGRAMMING; LOGIC DESIGN; NATURAL FREQUENCIES; OPTIMIZATION;

FLASH MEMORY;

EID: 25844515297     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Bauer, M. et al., "A Multilevel-cell 32Mb Flash Memory," ISSCC Dig. Tech. Papers, pp.132-133, Feb., 1995.
2. Elmhurst, D. et al., "A 1.8V 128Mb 125MHz Multi-level Cell Flash Memory with Flexible Read While Write," ISSCC Dig. Tech. Papers, pp. 286-287, Feb., 2003.
3. Lee, J. et al., "Effects of Floating-Gate Interference on NAND Flash Cell Operation," IEEE Electron Device Letters, pp.264-266. May, 2002.
4. Yoshikawa, M., "Impact of Cell Threshold Voltage Distribution in the Array of Flash Memories on Scaled and Multilevel Flash Cell Design," Symp. VLSI Technology, pp.240-241, June, 1996.