CMOS technologies in the 100 nm range for rad-hard front-end electronics in future collider experiments

Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

Volumn 596, Issue 1, 2008, Pages 107-112

  Re, Valerio ^a,c   Gaioni, Luigi ^b,c   Manghisoni, Massimo ^a,c   Ratti, Lodovico ^b,c   Speziali, Valeria ^b,c   Traversi, Gianluca ^a,c  

^a UNIVERSITY OF BERGAMO   (Italy)

^b UNIVERSITY OF PAVIA   (Italy)

^c INFN SEZIONE DI PAVIA   (Italy)

Author keywords

CMOS; Device scaling; Front end; Noise; Readout electronics

Indexed keywords

ANALOG CIRCUITS; DEGRADATION; DETECTORS; ELECTRON TUNNELING; INTEGRATED CIRCUITS; IONIZING RADIATION; MACHINE DESIGN; RADIATION; RADIATION DETECTORS; RADIATION SHIELDING; RADIOACTIVITY; SILICON; SILICON DETECTORS;

CMOS; DEVICE SCALING; FRONT-END; NOISE; READOUT ELECTRONICS;

CMOS INTEGRATED CIRCUITS;

EID: 54549125869     PISSN: 01689002     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.nima.2008.07.058     Document Type: Article

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