MPS: Miss-path scheduling for multiple-issue processors

IEEE Transactions on Computers

Volumn 47, Issue 12, 1998, Pages 1382-1397

  Banerjia, Sanjeev ^b   Sathaye, Sumedh W ^c   Menezes, Kishore N ^d   Conte, Thomas M ^a,e  

^a IEEE

^b HEWLETT PACKARD LABORATORIES   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

^d INTEL CORPORATION   (United States)

^e North Carolina State University   (United States)

Author keywords

Instruction level parallelism; Miss path scheduling; Multiple instruction issue; Schedule cache

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; RESPONSE TIME (COMPUTER SYSTEMS); SCHEDULING;

INSTRUCTION LEVEL PARALLELISM; MISS PATH SCHEDULING; MULTIPLE ISSUE PROCESSORS;

PIPELINE PROCESSING SYSTEMS;

EID: 0032290843     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.737684     Document Type: Article

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