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Volumn 24, Issue 2, 1996, Pages 187-206

Hardware-based profiling: An effective technique for profile-driven optimization

Author keywords

Branch handling; Compiler optimization; Microarchitecture; Profiling

Indexed keywords

COMPUTER ARCHITECTURE; OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

EID: 0030130138     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF03356747     Document Type: Article
Times cited : (24)

References (26)
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    • Yeh, T.1    Patt, Y.N.2
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    • A comparison of dynamic branch predictors that use two levels of branch history
    • Ann Arbor, Michigan, May
    • T. Yeh and Y. N. Patt, A comparison of dynamic branch predictors that use two levels of branch history, in Proc. 20th Ann. Int'l. Symp. Computer Architecture, Ann Arbor, Michigan, pp. 257-266 (May 1993).
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    • Yeh, T.1    Patt, Y.N.2
  • 16
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.