Gate insulator inhomogeneity in thin film transistors having a polycrystalline silicon layer prepared directly by catalytic chemical vapor deposition at a low temperature

Japanese Journal of Applied Physics, Part 2: Letters

Volumn 46, Issue 45-49, 2007, Pages

  Cho, Hyun Jun ^a   Hong, Wan Shick ^a   Lee, Sung Hyun ^a   Kim, Tae Hwan ^a   Lee, Kyung Min ^a   Park, Kyung Bae ^b   Jung, Ji Sim ^b   Kwon, Jang Yeon ^b  

^a University of Seoul   (South Korea)

^b Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

As deposited polycrystalline silicon; Catalytic chemical vapor deposition (Cat CVD); Crystallinity; Low temperature deposition; Thin film transistor (TFT)

Indexed keywords

DEPOSITION; FILM PREPARATION; POLYSILICON; SEMICONDUCTING SILICON COMPOUNDS; SILICON; THICK FILMS; THIN FILM DEVICES; THIN FILM TRANSISTORS; THIN FILMS; TRANSISTORS; VAPORS;

AS-DEPOSITED POLYCRYSTALLINE SILICON; CATALYTIC CHEMICAL VAPOR DEPOSITION (CAT-CVD); CRYSTALLINITY; LOW TEMPERATURE DEPOSITION; THIN FILM TRANSISTOR (TFT);

CHEMICAL VAPOR DEPOSITION;

EID: 54249159659     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.46.L1228     Document Type: Article

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