Fast bit gather, bit scatter and bit permutation instructions for commodity microprocessors

Journal of Signal Processing Systems

Volumn 53, Issue 1-2 SPEC. ISS., 2008, Pages 145-169

  Hilewitz, Yedidya ^a   Lee, Ruby B ^a  

^a Princeton University   (United States)

Author keywords

Algorithm acceleration; Bioinformatics; Bit gather; Bit manipulations; Bit scatter; Compression; Cryptology; Instruction set architecture; ISA; Microprocessors; Pack; Parallel deposit; Parallel extract; Pattern matching; Permutations; Steganography; Unpack

Indexed keywords

BIOINFORMATICS; COMPACTION; DEPOSITS; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; PACKING; PATTERN MATCHING; RANDOM NUMBER GENERATION; REDUCED INSTRUCTION SET COMPUTING; STEGANOGRAPHY;

BIT MANIPULATION; CRYPTOLOGY; INSTRUCTION SET ARCHITECTURE; PARALLEL EXTRACT; PERMUTATIONS; UNPACK;

PARALLEL PROCESSING SYSTEMS;

EID: 54249086611     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-008-0212-8     Document Type: Conference Paper

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