Fast bit compression and expansion with parallel extract and parallel deposit instructions

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2006, Pages 65-70

  Hilewitz, Yedidya ^a   Lee, Ruby B ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; DATA COMPRESSION; NETWORKS (CIRCUITS); REDUCED INSTRUCTION SET COMPUTING;

BIT MANIPULATION; BUTTERFLY NETWORK CIRCUITS; INSTRUCTION SET ARCHITECTURE; INSTRUCTION SET ARCHITECTURES;

MICROPROCESSOR CHIPS;

EID: 34547443955     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2006.33     Document Type: Conference Paper

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