Single-cycle bit permutations with MOMR execution

Journal of Computer Science and Technology

Volumn 20, Issue 5, 2005, Pages 577-585

  Lee, Ruby B ^a,c   Yang, Xiao ^a   Shi, Zhi Jie Jerry ^b,d,e,f  

^a Princeton University   (United States)

^b University of Connecticut   (United States)

^c PRINCETON UNIVERSITY   (United States)

^d UNIVERSITY OF CONNECTICUT   (United States)

^e ACM   (United States)

^f IEEE   (United States)

Author keywords

Bit permutations; Cryptographic acceleration; Cryptography; Datarich execution; High performance secure computing; Instruction set architecture; ISA; MOMR; Multi word operation; Permutation; Processor; Security

Indexed keywords

BIT PERMUTATIONS; CRYPTOGRAPHIC ACCELERATION; DATARICH EXECUTION; HIGH PERFORMANCE SECURE COMPUTING; INSTRUCTION SET ARCHITECTURE; ISA; MOMR; MULTI-WORD OPERATION; PERMUTATION;

ALGORITHMS; DATA STORAGE EQUIPMENT; PUBLIC KEY CRYPTOGRAPHY; REDUCED INSTRUCTION SET COMPUTING; SECURITY OF DATA;

PROGRAM PROCESSORS;

EID: 33644600006     PISSN: 10009000     EISSN: None     Source Type: Journal    
DOI: 10.1007/s11390-005-0577-0     Document Type: Conference Paper

References (23)

1. Schneier B. Applied Cryptography. 2nd Ed., John Wiley & Sons, Inc., 1996.
2. NIST (National Institute of Standards and Technology). Advanced Encryption Standard (AES). FIPS Pub. 197, 2001.
3. Lee R B, Shi Z, Yang X. Efficient permutation instructions for fast software cryptography. IEEE Micro, 2001, 21(6): 56-69.
4. Yang X, Vachharajani M, Lee R B. Fast subword permutation instructions based on butterfly networks. In Proc. SPIE 2000, January 2000, pp.80-86.
5. Yang X, Lee R B. Fast subword permutation instructions using omega and flip network stages. In Proc. the Int. Conf. Computer Design, September 2000, pp.15-22.
6. Shi Z, Lee R B. Bit permutation instructions for accelerating software cryptography. In Proc. the IEEE Int. Conf. Application-Specific Systems, Architectures and Processors, July 2000, pp.138-148.
7. McGregor J P, Lee R B. Architectural enhancements for fast subword permutations with repetitions in cryptographic applications. In Proc. the Int. Conf. Computer Design, September 2001, pp.453-461.
8. Lee R B. Subword parallelism with MAX-2. IEEE Micro, August 1996, 16(4): 51-59.
9. Diefendorff K et al. Alti Vec extension to PowerPC accelerates media processing. IEEE Micro, March 2000, 20(2): 85-95.
10. IA-64 application developer's architecture guide. Intel Corp., May 1999.
11. Princeton Architecture Lab for Multimedia and Security. http://palms.ee.princeton.edu/.
12. Burke J, McDonald J, Austin T. Architectural support for fast symmetric-key cryptography. In Proc. ASPLOS 2000, November 2000, pp.178-189.
13. Wu L, Weaver C, Austin T. CryptoManiac: A fast flexible architecture for secure communication. In Proc. the 28th Int. Symp. Computer Architecture, June 2001, pp.110-119.
14. Lee R B, Shi Z, Yang X. How a processor can permute n bits in O(1) cycles. In Proc. Hot Chips 14 -A Symposium on High Performance Chips, August 2002.
15. Lee R B, Yang X, Shi Z J. Validating word-oriented processors for bit and multi-word operations. In Proc. the Asia-Pacific Computer Systems Architecture Conference, 2004, pp.473-488.
16. Palacharla S, Jouppi N P, Smith J E. Complexity-effective superscalar processors. In Proc. the 24th Annual Int. Symp. Computer Architecture, 1997, pp.206-218.
17. Farell J A, Fischer T C. Issue logic for a 600-MHz out-of-order execution microprocessor. IEEE Journal of Solid-State Circuits, May 1998, 33(5): 707-712.
18. Onder S, Gupta R. Superscalar execution with direct data forwarding. In Proc. the 1998 ACM/IEEE Conf. Parallel Architectures and Compilation Techniques, 1998, pp.130-135.
19. Henry D S, Kuszmaul B C, Loh G H, Sami R. Circuits for wide-window superscalar processors. In Proc. the 27th Annual Int. Symp. Computer Architecture, 2000, pp.236-247.
20. Canal R, Gonzalez A. A Low-complexity issue logic. In Proc. the 14th Int. Conf. Supercomputing, 2000, pp.327-335.
21. Stark J, Brown M D, Patt Y N. On pipelining dynamic instruction scheduling logic. In Proc. the 33rd Annual ACM/IEEE Int. Symp. Microarchitecture, 2000, pp.57-66.
22. Brown M D, Stark J, Patt Y N. Select-free instruction scheduling logic. In Proc. the 34th ACM/IEEE Int. Symp. Microarchitecture, December 2001, pp.204-213.
23. Fiskiran A M, Lee R B. Evaluating instruction set extensions for fast arithmetic on binary finite fields. In Proc. the Int. Conf. Application-Specific Systems, Architectures, and Processors (ASAP), September 2004, pp.125-136.