A review of large parallel counter designs

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Volumn , Issue , 2004, Pages 89-98

  Swartzlander Jr , Earl E ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FAST MULTIPLIERS; PARALLEL COUNTERS; THRESHOLD GATES;

CMOS INTEGRATED CIRCUITS; COUNTING CIRCUITS; FEEDBACK; SIGNAL PROCESSING; SWITCHING; THRESHOLD ELEMENTS; VLSI CIRCUITS;

FREQUENCY MULTIPLYING CIRCUITS;

EID: 4544296196     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. L. Dadda, "Some Schemes for Parallel Multipliers," Alta Frequenza, vol. 34, pp. 349-356, 1965.
2. Caxton C. Foster and Fred D. Stockton, "Counting Responders in an Associative Memory," IEEE Transactions on Computers, vol. C-20, pp. 1580-1583, 1971.
3. A. D. Falkoff, "Algorithms for Parallel Search Memories," Journal of the ACM, vol. 9, pp. 488-551, 1962.
4. H. Fleisher, Combinatorial Techniques for Performing Arithmetic and Logical Operations, Research Report RC-289, Yorktown Heights, NY: IBM Research Center, 1960.
5. D. Zhang, G. A. Jullien, W. C. Miller and Earl Swartzlander, Jr., "Arithmetic for Digital Neural Networks," Proceedings 10th Symposium on Computer Arithmetic, Grenoble, France, pp. 58-63, 1991.
6. Earl E. Swartzlander, Jr., "Parallel Counters," IEEE Transactions on Computers, vol. C-22, pp. 1021-1024, 1973.
7. Irving T. Ho and Tien Chi Chen "Multiple Addition by Residue Threshold Functions and Their Representation by Array Logic," IEEE Transactions on Computers, vol. C-22, pp. 762-767, 1973.
8. Antonin Svoboda, "Adder With Distributed Control," IEEE Transactions on Computers, vol. C-19, pp. 749-751, 1970.
9. Ben C. Drerup and Earl E. Swartzlander, Jr., "Fast Multiplier Bit-Product Matrix Reduction Using Bit-Ordering and Parity Generation," Journal of VLSI Signal Processing, vol. 7, pp. 249-257, 1994.
10. Robert F. Jones, Jr. and Earl E. Swartzlander, Jr., "Parallel Counter Implementation" Journal of VLSI Signal Processing, vol. 7, pp. 223-232, 1994.
11. Mayur Mehta, Vijay Parmar and Earl Swartzlander, Jr., "High-Speed Multiplier Design Using Multi-Input Counter and Compressor Circuits," Proceedings 10th Symposium on Computer Arithmetic, Grenoble, France, pp. 43-50, 1991.