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Volumn 11, Issue 3, 2003, Pages 325-335

Architectural techniques for accelerating subword permutations with repetitions

Author keywords

Cryptography; Encryption; Instruction set architecture; Permutation; Permutation instruction; Processor architecture; Subword parallelism; Subword permutation

Indexed keywords

ALGORITHMS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING;

EID: 0041418161     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.812318     Document Type: Article
Times cited : (12)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.