A compact approach to on-chip interconnect heat conduction modeling using the finite element method

Journal of Electronic Packaging

Volumn 130, Issue 3, 2008, Pages 0310011-0310018

  Gurrum, Siva P ^a   Joshi, Yogendra K ^b   King, William P ^c   Ramakrishna, Koneru ^d   Gall, Martin ^d  

^a TEXAS INSTRUMENTS   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c University of Illinois at Urbana Champaign   (United States)

^d FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HEAT CONDUCTION; INTEGRATED CIRCUIT INTERCONNECTS; JOULE HEATING;

COMPACT MODEL; ELECTRONIC TECHNOLOGIES; HEAT CONDUCTION MODELS; HIGH CURRENT DENSITIES; HIGHEST TEMPERATURE; ON-CHIP INTERCONNECTS; SELF-HEATING; SHRINKING FEATURE SIZES; TECHNOLOGY NODES; TEMPERATURE RISE;

FINITE ELEMENT METHOD;

EID: 52649099504     PISSN: 10437398     EISSN: 15289044     Source Type: Journal    
DOI: 10.1115/1.2957318     Document Type: Article

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