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Volumn 34, Issue 12 SPEC.ISS., 2003, Pages 1153-1165

HotSpot: A dynamic compact thermal model at the processor-architecture level

Author keywords

Computer architecture; Dynamic compact models; Thermal models

Indexed keywords

CAPACITANCE; COMPUTATIONAL METHODS; COMPUTER SIMULATION; HEAT LOSSES; HEAT RESISTANCE; NETWORKS (CIRCUITS); PROGRAM PROCESSORS; THERMAL EFFECTS;

EID: 0242406726     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(03)00206-4     Document Type: Conference Paper
Times cited : (93)

References (30)
  • 5
    • 0036902415 scopus 로고    scopus 로고
    • Global coupled EM-electrical-thermal simulation and experimental validation for a spatial power combining MMIC array
    • Batty W., et al. Global coupled EM-electrical-thermal simulation and experimental validation for a spatial power combining MMIC array. IEEE Transactions on Microwave Theory and Techniques. 2002;2820-2833.
    • (2002) IEEE Transactions on Microwave Theory and Techniques , pp. 2820-2833
    • Batty, W.1
  • 8
    • 0027850837 scopus 로고
    • Electrothermal simulation of integrated circuits
    • Lee S.S., Allstot D.J. Electrothermal simulation of integrated circuits. IEEE Journal of Solid-state Circuits. 28:(12):1993;1283-1293.
    • (1993) IEEE Journal of Solid-state Circuits , vol.28 , Issue.12 , pp. 1283-1293
    • Lee, S.S.1    Allstot, D.J.2
  • 15
    • 0038027393 scopus 로고    scopus 로고
    • Thermal management
    • F. Kreith. (Ed.), Boca Raton, FL: CRC Press
    • Krum A. Thermal management. Kreith F. The CRC Handbook of Thermal Engineering. 2000;2.1-2.92 CRC Press, Boca Raton, FL.
    • (2000) The CRC Handbook of Thermal Engineering , pp. 21-292
    • Krum, A.1
  • 16
    • 0003450887 scopus 로고    scopus 로고
    • Cacti 3.0: An integrated cache timing, power and area model
    • Compaq Western Research Laboratory, Feb.
    • P. Shivakumar, N.P. Jouppi, Cacti 3.0: an integrated cache timing, power and area model, Technical Report, Compaq Western Research Laboratory, Feb., 2001.
    • (2001) Technical Report
    • Shivakumar, P.1    Jouppi, N.P.2
  • 21
    • 84949752476 scopus 로고    scopus 로고
    • CPU Info Center
    • MIPS R10000 die photo, from website: CPU Info Center, http://bwrc.eecs.berkeley.edu/CIC/die_photos/#mips.
    • MIPS R10000 Die Photo
  • 22
    • 0242555930 scopus 로고    scopus 로고
    • CPU Info Center
    • Intel Pentium die photo, from website: CPU Info Center, http://bwrc.eecs.berkeley.edu/CIC/die_photos/pentium.gif.
    • Intel Pentium Die Photo
  • 23
    • 0032290916 scopus 로고    scopus 로고
    • Circuit implementation of a 600 MHz superscalar RISC microprocessor
    • Matson M., et al. Circuit implementation of a 600 MHz superscalar RISC microprocessor. Computer Design: VLSI in Computers and Processors. 26:(2):1998;104-110.
    • (1998) Computer Design: VLSI in Computers and Processors , vol.26 , Issue.2 , pp. 104-110
    • Matson, M.1
  • 25
    • 29144465623 scopus 로고    scopus 로고
    • Standard Performance Evaluation Corporation, SPEC CPU2000 Benchmarks, http://www.specbench.org/osg/cpu2000.
    • SPEC CPU2000 Benchmarks


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.