Application specific low latency instruction cache for NAND flash memory based embedded systems

2008 Symposium on Application Specific Processors, SASP 2008

Volumn , Issue , 2008, Pages 69-74

  Lee, Kwangyoon ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS LATENCY; ACCESS TIME; APPLICATION-SPECIFIC; APPLICATION-SPECIFIC PROCESSORS; CACHE ARCHITECTURE; CODE STORAGE; HIGH CAPACITY; HOT SPOTTING; INSTRUCTION CACHES; LOW-LATENCY; NAND FLASH MEMORIES; NEGATIVE IMPACTS; ORDERS-OF-MAGNITUDE; PRE-FETCHING; PREFETCHING ALGORITHM; PREFETCHING TECHNIQUES; PROPOSED ARCHITECTURES; STORAGE SOLUTIONS; TEMPORAL DISTANCE;

CACHE MEMORY; CODES (STANDARDS); CODES (SYMBOLS); COMPUTER PROGRAMMING LANGUAGES; DATA STORAGE EQUIPMENT; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; NAND CIRCUITS;

FLASH MEMORY;

EID: 52349112748     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SASP.2008.4570788     Document Type: Conference Paper

References (13)

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