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Volumn , Issue , 2002, Pages 181-186

Energy frugal tags in reprogrammable I-caches for application-specific embedded processors

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; CODES (SYMBOLS); COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; ENERGY DISSIPATION; OPTIMIZATION; PROGRAM PROCESSORS; SOFTWARE ENGINEERING;

EID: 0036042331     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774789.774826     Document Type: Conference Paper
Times cited : (7)

References (18)
  • 1
    • 0033358971 scopus 로고    scopus 로고
    • Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
    • August
    • (1999) ISLPED , pp. 70-75
    • Ghose, K.1    Kamble, M.B.2
  • 7
    • 85008057924 scopus 로고    scopus 로고
    • Performance and power effectiveness in embedded processors - Customizable partitioned caches
    • November
    • (2001) IEEE TCAD , vol.20 , Issue.11 , pp. 1309-1318
    • Petrov, P.1    Orailoglu, A.2
  • 8
    • 0029182643 scopus 로고
    • Reducing the frequency of tag compares for low power I-cache designs
    • October
    • (1995) SLPE , pp. 57-62
    • Panwar, R.1    Rennels, D.2
  • 17
    • 0003465202 scopus 로고    scopus 로고
    • The simplescalar tool set, version 2.0
    • Technical Report 1342, University of Wisconsin-Madison, CS Department, June
    • (1997)
    • Burger, D.1    Austin, T.M.2
  • 18
    • 0003946111 scopus 로고    scopus 로고
    • An integrated cache timing and power model
    • Technical report, Western Research Lab.
    • (1999)
    • Reinman, G.1    Jouppi, N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.