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Volumn 43, Issue 9, 2008, Pages 2120-2133

Design and comparison of three 20-Gb/s backplane transceivers for duobinary, PAM4, and NRZ data

Author keywords

Backplane transceiver; Bit error rate (BER); Duobinary; Non return to zero (NRZ); Pulse amplitude modulation (PAM4)

Indexed keywords

OPTICAL DESIGN;

EID: 52249102222     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2001934     Document Type: Article
Times cited : (126)

References (14)
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    • J. Sinsky et al, "10 Gb/s duobinary signaling over electrical backplanes-Experimental results and discussion," Lucent Technologies, Bell Labs [Online]. Available: http://www.ieee802.org/3/ap/public/jul04/ sinsky_01_0704.pdf
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    • A 22-Gb/s PAM-4 receiver in 90-nm. CMOS SOI technology
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    • H. Tao et al., 40-43-Gb/s OC-768 16:1 MUX/CMU chipset with SFI-5 compliance, IEEE J. Solid-State Circuits, 38, no. 12, pp. 2169-2180, Dec. 2003.
    • H. Tao et al., "40-43-Gb/s OC-768 16:1 MUX/CMU chipset with SFI-5 compliance," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2169-2180, Dec. 2003.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.