A 75-GHz PLL in 90-nm CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 432-434

  Lee, Jri ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY BANDS; INTEGRATED CIRCUIT TESTING; NANOELECTRONICS; OSCILLATORS (ELECTRONIC);

REFERENCE SIDE BANDS; SSB MIXERS;

PHASE LOCKED LOOPS;

EID: 34548011654     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373479     Document Type: Conference Paper

References (3)

1. H.R. Rategh and T.H. Lee, "Superharmonic Injection-Locked Frequency Dividers," IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June, 1999.
2. Jri Lee and Behzad Razavi, "A 40-GHz Frequency Divider in 0.18μm CMOS Technology," IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, April, 2004.
3. Jri Lee, "High-Speed Circuit Designs for Transmitters in Broadband Data Links," IEEE J. Solid-State Circuits, vol. 41, pp. 1004-1015, May, 2006.