A 20Gb/s duobinary transceiver in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 101-103

  Lee, Jri ^a   Chen, Ming Shuan ^a   Wang, Huai De ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

TRANSCEIVERS;

90-NM CMOS; DUO-BINARY; ERROR FREE OPERATIONS; FULLY INTEGRATED; PRE CODERS;

CMOS INTEGRATED CIRCUITS;

EID: 49549105150     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523077     Document Type: Conference Paper

References (3)

1. Hari Shankar, Inphi, "Duobinary Modulation for Optical Systems", Accessed on Nov. 6, 2007, http://www.inphi-corp.com/products/ whitepapers/DuobinaryModulationForOpticalSystems.pdf.
2. Jri Lee, "A 75-GHz PLL in 90-nm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 432-433, Feb. 2007.
3. K. Yamaguchi, K. Sunaga, S. Kaeriyama, et al., "12Gb/s Duobinary Signaling with x2 Oversampled Edge Equalization," ISSCC Dig. Tech. Papers, pp. 70-71, Feb. 2005.