Scalable calculation of logical masking effects for selective hardening against soft errors

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008

Volumn , Issue , 2008, Pages 257-262

  Polian, Ilia ^a   Reddy, Sudhakar M ^b   Becker, Bernd ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

Selective hardening; Soft error protection

Indexed keywords

COST REDUCTION; ERROR ANALYSIS; ERROR CORRECTION; ERRORS; FAULT DETECTION; HARDENING; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); TECHNOLOGY; WINDOWS;

APPROXIMATE CALCULATIONS; CIRCUIT NODES; ERROR PROBABILITIES; MASKING EFFECTS; RUN TIMES; SELECTIVE HARDENING; SOFT ERROR PROTECTION; SOFT ERROR RATES; SOFT ERRORS; VLSI TECHNOLOGIES;

PROBABILITY;

EID: 51849141355     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2008.22     Document Type: Conference Paper

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