A cache-defect-aware code placement algorithm for improving the performance of processors

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 995-1001

  Ishihara, Tohru ^a   Fallah, Farzan ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CACHE MEMORY; COMPUTATIONAL METHODS; FAULT TOLERANT COMPUTER SYSTEMS; FAULT TREE ANALYSIS; PROGRAM COMPILERS;

CACHE DEFECT AWARE CODES; COMPILER BASED TECHNIQUES; DEFECTIVE CACHE MEMORY; PERFORMANCE DEGRADATION;

MICROPROCESSOR CHIPS;

EID: 33751440059     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560207     Document Type: Conference Paper

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