Two-trap model for low voltage stress-induced leakage current in ultrathin SiON dielectrics

Journal of Applied Physics

Volumn 104, Issue 5, 2008, Pages

  Nicollian, Paul E ^a   Krishnan, Anand T ^a   Reddy, Vijay K ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC DEVICES; DIELECTRIC FILMS; DIELECTRIC MATERIALS; EXCAVATION; GATE DIELECTRICS; LEAKAGE CURRENTS; METALS; MOLECULAR BEAM EPITAXY; MOSFET DEVICES; SEMICONDUCTING INDIUM; SEMICONDUCTOR DEVICES; TUNNELING (EXCAVATION); ULTRATHIN FILMS;

CONTACT INTERFACES; DOMINANT TRANSPORT; ELECTRICAL STRESSING; GATE CURRENTS; I-V CHARACTERISTICS; INTERFACE STATES; INTERFACE TRAPPING; LOW VOLTAGES; METAL-OXIDE SEMICONDUCTORS; N -CHANNEL; STRESS-INDUCED LEAKAGE CURRENT; TRAP ASSISTED TUNNELLING; TRAP STATES; TUNNELING PROCESSES; ULTRA-THIN DIELECTRIC FILMS; ULTRATHIN SION;

CURRENT VOLTAGE CHARACTERISTICS;

EID: 51849109873     PISSN: 00218979     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.2969791     Document Type: Article

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