A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 4082-4085

  Wu, Chia Tsun ^a   Wang, Wei ^a   Wey, I Chyn ^a   Wu, An Yeu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

FREQUENCY ESTIMATION; OPTIMIZATION; SWITCHING SYSTEMS; SYNCHRONIZATION;

BINARY FREQUENCY-SEARCH ALGORITHM; FREQUENCY ESTIMATION ALGORITHM; FREQUENCY MULTIPLICATION SWITCHES;

ALGORITHMS;

EID: 34547247708     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Takamoto Watanabe and Shigenori Yamauchi, "An All-Digital PLL for Frequency Multiplication by 4 to 1024 With Seven-Cycle Lock Time," IEEE Journa of Solid-State Circuit, vol. 38, no. 2, February 2003.
2. C. Chung and C. Lee, "An all-digital phase-locked loop for high-speed clock generation," IEEE International Symposium on Circuits and Systems, vol. 3, pp.26-29, May 2002.
3. I. Hwang, S Lee, S. Lee, and S. Kim, "A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application," IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2000, pp. 168-169
4. T.-Y. Hsu, C.-C. Wang, and C.-Y. Lee, "Design and analysis of portable high-speed clock generator," IEEE Trans. Circuits Syst. II, vlo. 48, pp. 367-375, Apr. 2001.
5. H.-T Ahn and D.J. Allstot, "A low-jitter 1.9V CMOS PLL for ultra-SPARC microprocessor applications," IEEE K. Solid-State Circuits, vol. 35, pp. 450-454, May 1999.
6. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, and An-Yeu (Andy) Wu, "A Scalable DCO Design for Portable ADPLL Designs," IEEE International Symposium on Circuits and Systems, pp. 5449-5452, May 2005.