Probabilistic self-adaptation of nanoscale CMOS circuits: Yield maximization under increased intra-die variations

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 711-716

  Ashouei, Maryam ^a   Nisar, Muhammad M ^a   Chatterjee, Abhijit ^a   Singh, Adit D ^b   Diril, Abdulkadir U ^c  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AUBURN UNIVERSITY   (United States)

^c GiQuila Corporation

Author keywords

Process variation; Reconfiguration; Yield improvement

Indexed keywords

CIRCUIT TIMING; CMOS TECHNOLOGIES; DELAY TESTING; DIE-TO-DIE VARIATIONS; DIGITAL CONTROLS; INTERNATIONAL CONFERENCES; LARGE DELAYS; NANO-SCALE CMOS; NEW APPROACHES; PROCESS VARIABILITY; PROGRAMMABLE GATES; RECONFIGURATION PROCESSES; RECONFIGURATION TIME; SELF ADAPTATION; STATISTICAL CORRELATIONS; VLSI DESIGNS; YIELD IMPROVEMENTS;

ARSENIC COMPOUNDS; COMPUTER PROGRAMMING LANGUAGES; CORRELATION METHODS; DIES; DIGITAL CONTROL SYSTEMS; ELECTRIC CURRENTS; INTEGRATED CIRCUITS; NETWORKS (CIRCUITS); STATISTICAL METHODS; TIME MEASUREMENT; TIMING CIRCUITS; ULTRASONIC TRANSDUCERS;

EMBEDDED SYSTEMS;

EID: 48349114364     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.130     Document Type: Conference Paper

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