Programmable threshold voltage using quantum dot transistors for low-power mobile computing

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 3350-3353

  Wang, Shuo ^a   Dai, Jianwei ^a   Hasaneen, El Sayed ^b   Wang, Lei ^a   Jain, Faquir ^a  

^a UNIVERSITY OF CONNECTICUT   (United States)

^b MINIA UNIVERSITY   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; EFFICIENCY; ENERGY EFFICIENCY; HAND HELD COMPUTERS; OPTICAL WAVEGUIDES; OPTIMIZATION; QUANTUM ELECTRONICS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICES; SEMICONDUCTOR QUANTUM DOTS; TECHNICAL PRESENTATIONS; THRESHOLD VOLTAGE; TRANSISTORS;

INTERNATIONAL SYMPOSIUM; POWER CONSUMPTION; POWER-PERFORMANCE;

MOBILE COMPUTING;

EID: 51749107197     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4542176     Document Type: Conference Paper

References (15)

1. S. Narendra, D. Blaauw, A. Devgan, and F. Najm, "Leakage issues in IC design: Trends, estimation and avoidance," Int'l. Conf. on CAD, pp. 11, 2003.
2. S. Mutah, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS," IEEE Jnl. of Solid-State Circuits, vol. 30, pp. 847-853, 1995.
3. 2 2 - D discrete cosine transform core processor with variable-threshold-voltage scheme," Int'l. Solid-State Circuits Conf., pp. 166-167, 1996.
4. T H CMOS (MVCMOS) for low power applications," Int'l. Symp. on Circuits and Systems, pp. 430-435, 1999.
5. L. Wei, Z. Chen, K. Roy, Y. Ye, and V. De, "Mixed-Vth (MVT) CMOS circuit design methodology for low power applications," Design Automation Conf., pp. 430-435, 1999.
6. C. Fujihashi, T. Yukiya, and A. Asenov, "Electron and Hole Current Characteristics of n-i-p-Type Semiconductor Quantum Dot Transistor," IEEE Trans. Nanotechnology, vol 6, no. 3, pp. 320-327, 2007.
7. M. She, T. J. King, "Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance," IEEE Trans. on Electron Devices, vol. 50, no. 9, pp. 1934-1940, 2003.
8. El-Sayed Hasaneen, E. Heller, R. Bansal, W. Huang, and F. Jian "Modeling of nonvolatile floating gate quantum dot memory," Solid-State Electronics, vol. 48, pp. 2055-2059, 2004.
9. Berkeley Device Group, http://www-device.eecs.berkeley.edu/~bsim3/ bsim4.html.
10. S. Kinoshita, T. Morie, M. Nagata, and A. Iwata, "A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution," IEEE Jnl. of Solid-State Circuits, vol. 36, no. 8, pp. 1286-1290, 2001.
11. M. Hooper, "Submicron CMOS programmable analog floating-gate circuits and arrays using DC-DC converters," Thesis, Georgia Institute of Technology, 2005.
12. T H for low-power and high-speed applications," Asia and South Pacific Design Automation Conf., pp. 469-474, 2000.
13. S. Haykin, Adaptive Filter Theory, Prentice Hall, 1996.
14. M. Hansen, H. Yalcin, and J. P. Hayes, ISCAS High-Level Models, http://www.eecs.umich.edu/~jhayes/iscas.restore/74283.html.
15. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," CICC, pp. 201-204, 2000.