VLSI communication architecture for stochastically pulse-encoded analog signals

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1996, Pages 401-404

  Abusland, Aanen ^a   Lande, Tor S ^a   Hovin, Mats ^a  

^a UNIVERSITY OF OSLO   (Norway)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT THEORY; COMPUTER HARDWARE; COMPUTER NETWORKS; ENCODING (SYMBOLS); NETWORK PROTOCOLS; QUEUEING THEORY; RANDOM PROCESSES; TIME DIVISION MULTIPLEXING; VLSI CIRCUITS;

COMPUTER COMMUNICATION PROTOCOLS; COMPUTER NETWORK THEORY; INTERCHIP COMMUNICATION; STOCHASTICALLY PULSE ENCODED ANALOG SIGNALS; VLSI COMMUNICATION ARCHITECTURE;

ELECTRIC NETWORK TOPOLOGY;

EID: 0029720957     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)