-
4
-
-
0015651305
-
"A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations"
-
Aug
-
P.M. Kogge and H.S. Stone, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations," IEEE Trans. Computers, vol. 22, no. 8, pp. 786-792, Aug. 1973.
-
(1973)
IEEE Trans. Computers
, vol.22
, Issue.8
, pp. 786-792
-
-
Kogge, P.M.1
Stone, H.S.2
-
5
-
-
84976772007
-
"Parallel Prefix Computation"
-
Oct
-
R.E. Ladner and M.J. Fisher, "Parallel Prefix Computation," J. ACM vol. 27, no. 4, pp. 831-838, Oct. 1980.
-
(1980)
J. ACM
, vol.27
, Issue.4
, pp. 831-838
-
-
Ladner, R.E.1
Fisher, M.J.2
-
6
-
-
0020102009
-
"A Regular Layout for Parallel Adders"
-
Mar
-
R.P. Brent and H.T. Kung, "A Regular Layout for Parallel Adders," IEEE Trans. Computers, vol. 31, no. 3, pp. 260-264, Mar. 1982.
-
(1982)
IEEE Trans. Computers
, vol.31
, Issue.3
, pp. 260-264
-
-
Brent, R.P.1
Kung, H.T.2
-
8
-
-
0034864101
-
"A Family of Adders"
-
pp. 30-34, Apr. Reprinted in ARITH-15
-
S. Knowles, "A Family of Adders," Proc. 14th Symp. Computer Arithmetic, pp. 30-34, Apr. 1999. Reprinted in ARITH-15, pp. 277-281.
-
(1999)
Proc. 14th Symp. Computer Arithmetic
, pp. 277-281
-
-
Knowles, S.1
-
10
-
-
27944436914
-
"Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders"
-
June
-
V.G. Oklobdzija et al., "Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders," Proc. 16th Symp. Computer Arithmetic, pp. 15-22, June 2003.
-
(2003)
Proc. 16th Symp. Computer Arithmetic
, pp. 15-22
-
-
Oklobdzija, V.G.1
-
11
-
-
0000760312
-
"High-Speed Binary Adder"
-
May
-
H. Ling, "High-Speed Binary Adder," IBM J. R&D, vol. 25, pp. 156-166, May 1981.
-
(1981)
IBM J. R&D
, vol.25
, pp. 156-166
-
-
Ling, H.1
-
12
-
-
0024073321
-
"Variants of an Improved Carry-Lookahead Adder"
-
R.W. Doran, "Variants of an Improved Carry-Lookahead Adder," IEEE Trans. Computers, vol. 37, pp. 1110-1113, 1988.
-
(1988)
IEEE Trans. Computers
, vol.37
, pp. 1110-1113
-
-
Doran, R.W.1
-
13
-
-
0024717368
-
"Recursive Equations for Hardwired Binary Adders"
-
Aug
-
S. Vassiliadis, "Recursive Equations for Hardwired Binary Adders," J. Electronics, vol. 67, no. 2, pp. 201-213, Aug. 1989.
-
(1989)
J. Electronics
, vol.67
, Issue.2
, pp. 201-213
-
-
Vassiliadis, S.1
-
14
-
-
0001138583
-
"High-Speed Addition in CMOS"
-
Dec
-
N.T. Quach and M.J. Flynn, "High-Speed Addition in CMOS," IEEE Trans. Computers, vol. 41, no. 12, pp. 1612-1615, Dec. 1992.
-
(1992)
IEEE Trans. Computers
, vol.41
, Issue.12
, pp. 1612-1615
-
-
Quach, N.T.1
Flynn, M.J.2
-
16
-
-
0032681048
-
"Intermediate Variable Encodings that Enable Multiplexor Based Implementations of Two Operand Addition"
-
Apr
-
D. Phatak and I. Koren, "Intermediate Variable Encodings that Enable Multiplexor Based Implementations of Two Operand Addition," Proc. Symp. Computer Arithmetic, pp. 22-29, Apr. 1999.
-
(1999)
Proc. Symp. Computer Arithmetic
, pp. 22-29
-
-
Phatak, D.1
Koren, I.2
-
18
-
-
0036098656
-
"The Design of Hybrid Carry-Lookahead/ Carry-Select Adders"
-
Jan
-
Y. Wang, C. Pai, and X. Song, "The Design of Hybrid Carry-Lookahead/ Carry-Select Adders," IEEE Trans. Circuits and Systems II, vol. 49, no. 1, Jan. 2002.
-
(2002)
IEEE Trans. Circuits and Systems II
, vol.49
, Issue.1
-
-
Wang, Y.1
Pai, C.2
Song, X.3
-
19
-
-
14844362846
-
"Ling Adders in Standard CMOS Technologies"
-
Sept
-
C. Efstathiou, H.T. Vergos, and D. Nikolos, "Ling Adders in Standard CMOS Technologies," Proc. IEEE Int'l Conf. Electronics, Circuits, and Systems (ICECS), vol. 2, pp. 485-488, Sept. 2002.
-
(2002)
Proc. IEEE Int'l Conf. Electronics, Circuits, and Systems (ICECS)
, vol.2
, pp. 485-488
-
-
Efstathiou, C.1
Vergos, H.T.2
Nikolos, D.3
-
20
-
-
0026907993
-
"A Spanning Tree Carry Lookahead Adder"
-
Aug
-
T. Lynch and E. Swartzlander, "A Spanning Tree Carry Lookahead Adder," IEEE Trans Computers, vol. 41, no. 8, pp. 931-939, Aug. 1992.
-
(1992)
IEEE Trans Computers
, vol.41
, Issue.8
, pp. 931-939
-
-
Lynch, T.1
Swartzlander, E.2
-
21
-
-
0033292813
-
"A 1.0-nsec 32-bit Prefix Tree Adder in 0. 25-mμm Static CMOS"
-
Aug
-
A. Goldovsky et al., "A 1.0-nsec 32-bit Prefix Tree Adder in 0. 25-mμm Static CMOS," Proc. Midwest Symp. Circuits and Systems, vol. 2, pp. 608-612, Aug. 1999.
-
(1999)
Proc. Midwest Symp. Circuits and Systems
, vol.2
, pp. 608-612
-
-
Goldovsky, A.1
|