A delay-line based DCO for multimedia applications using digital standard cells only

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Roth, Eric ^a   Thalmann, Markus ^a   Felber, Norbert ^a   Fichtner, Wolfgang ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POTENTIAL; JITTER; MULTIMEDIA SYSTEMS; PHASE LOCKED LOOPS; THERMAL EFFECTS; TIMING CIRCUITS;

DIGITAL CLOCK SYNTHESIZER; DIGITAL DELAY LINE; DIGITAL STANDARD CELL; DIGITALLY CONTROLLED OSCILLATOR; DIRECT DIGITAL SYNTHESIS; RING OSCILLATOR;

OSCILLATORS (ELECTRONIC);

EID: 0037968905     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. D. Mijuskovic et al., "Cell-Based Fully Integrated CMOS Frequency Synthesizers," IEEE J. Solid-State Circuits, vol. 29, pp. 271-279, Mar. 1994.
2. T.-Y. Hsu et al., "Design and Analysis of a Portable High-Speed Clock Generator," IEEE Tr. on Circuits and Systems-II, vol. 48, pp. 367-375, Apr. 2001.
3. D. Calbaza and Y. Savaria, "Direct Digital Frequency Synthesis of Low-Jitter Clocks," IEEE J. Solid-State Circuits, vol. 36, pp. 570-572, Mar. 2001.