SystemC transaction level models and RTL verification

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 90-92

  Swan, Stuart ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Hardware software co design; Hardware software co verification; RTL verification; SystemC; TLM; Transaction level model

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; MICROPROCESSOR CHIPS; VERIFICATION;

FRAGMENTATION; RTL; SYSTEMC; TRANSACTION LEVEL MODELS;

LOGIC DESIGN;

EID: 34250184304     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146937     Document Type: Conference Paper

References (3)

1. Chang, Cooke, Hunt, McNelly, Martin, Todd Surviving the SOC Revolution: A Guide to Platform-Based Design. Kluwer Academic Publishers, Boston, MA, 1999.
2. Grotker, Liao, Martin, Swan. System Design with SystemC. Kluwer Academic Publishers, Boston, MA, 2002.
3. Ghenassia, F., Transaction Level Modeling with SystemC. Springer, Dordrecht, Netherlands, 2005.