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Volumn , Issue , 2008, Pages 69-74

On bypassing blocking bugs during post-silicon validation

Author keywords

[No Author keywords available]

Indexed keywords

EUROPEAN; POST-SILICON; SILICON VERIFICATION;

EID: 51549089377     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2008.29     Document Type: Conference Paper
Times cited : (3)

References (17)
  • 5
    • 39749117563 scopus 로고    scopus 로고
    • On Using Lossless Compression of Debug Data in Embedded Logic Analysis
    • paper 18.3, October
    • E. Anis and N. Nicolici. On Using Lossless Compression of Debug Data in Embedded Logic Analysis. In Proceedings IEEE International Test Conference (ITC), pages 1-10, paper 18.3, October 2007.
    • (2007) Proceedings IEEE International Test Conference (ITC) , pp. 1-10
    • Anis, E.1    Nicolici, N.2
  • 7
    • 33745687487 scopus 로고    scopus 로고
    • Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
    • February
    • A. Hopkins and K. McDonald-Maier. Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores. IEEE Transactions on Computers, 55(2): 174-184, February 2006.
    • (2006) IEEE Transactions on Computers , vol.55 , Issue.2 , pp. 174-184
    • Hopkins, A.1    McDonald-Maier, K.2
  • 9
    • 51549083423 scopus 로고    scopus 로고
    • IEEE JTAG 1149.1-2001 Std. IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE Computer Society, 2001.
    • IEEE JTAG 1149.1-2001 Std. IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE Computer Society, 2001.
  • 13
    • 27844542862 scopus 로고    scopus 로고
    • An Embedded Debugging Architecture for SOCs
    • February
    • R. Leatherman and N. Stollon. An Embedded Debugging Architecture for SOCs. IEEE Potentials, 24(1):12-16, February 2005.
    • (2005) IEEE Potentials , vol.24 , Issue.1 , pp. 12-16
    • Leatherman, R.1    Stollon, N.2
  • 14
    • 0033343250 scopus 로고    scopus 로고
    • Design For (Physical) Debug For Silicon Microsurgery and Probing of Flip-Chip Packaged Integrated Circuits
    • September
    • R. Livengood and D. Medeiros. Design For (Physical) Debug For Silicon Microsurgery and Probing of Flip-Chip Packaged Integrated Circuits. In Proceedings IEEE International Test Conference (ITC), pages 877-882, September 1999.
    • (1999) Proceedings IEEE International Test Conference (ITC) , pp. 877-882
    • Livengood, R.1    Medeiros, D.2
  • 15
    • 0031186690 scopus 로고    scopus 로고
    • IC Failure Analysis: The Importance of Test and Diagnostics
    • July
    • D. P. Vallett. IC Failure Analysis: The Importance of Test and Diagnostics. IEEE Design and Test of Computers. 14(3):76-82, July 1997.
    • (1997) IEEE Design and Test of Computers , vol.14 , Issue.3 , pp. 76-82
    • Vallett, D.P.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.