-
2
-
-
51349094282
-
-
Steven N. Towle, Henning Braunisch, Chuan Hu, Richard D. Emery, and Gilroy J. Vandentop, Intel Corporation, Bumpless Build-Up Layer Packaging, ASME, 2002.
-
Steven N. Towle, Henning Braunisch, Chuan Hu, Richard D. Emery, and Gilroy J. Vandentop, Intel Corporation, "Bumpless Build-Up Layer Packaging", ASME, 2002.
-
-
-
-
3
-
-
0038012254
-
Development of Interconnect Technologies for Embedded Organic Packages
-
New Orleans, May 27-30
-
Sunohara, M, Murayama, K, Higashi, M and Shimizu, M, "Development of Interconnect Technologies for Embedded Organic Packages", 2003 Electronic Components and Technology Conference, New Orleans, May 27-30 (2003) pp. 1484-1489.
-
(2003)
2003 Electronic Components and Technology Conference
, pp. 1484-1489
-
-
Sunohara, M.1
Murayama, K.2
Higashi, M.3
Shimizu, M.4
-
4
-
-
84962234558
-
Polymers and Adhesives in Microelectronics and Photonics, 2nd International IEEE Conference
-
on 23-26 June 2002 Page(s):160, 164
-
Ostmann, A.; Neumann, A.; Weser, S.; Jung, E.; Bottcher, L.; Reichl, H., "Realization of a stackable package using chip in polymer technology". Polymers and Adhesives in Microelectronics and Photonics, 2nd International IEEE Conference on 23-26 June 2002 Page(s):160 - 164.
-
-
-
Ostmann, A.1
Neumann, A.2
Weser, S.3
Jung, E.4
Bottcher, L.5
Reichl, H.6
-
5
-
-
35348823057
-
Chip-last Embedded Active for System-On-Package (SOP)
-
Reno, May
-
Baik-Woo Lee, Venky Sundaram, Boyd Wiedenman, Chong K Yoon, Mahadevan Iyer and Rao R Tummala, "Chip-last Embedded Active for System-On-Package (SOP)", 2007 Electronic Components and Technology Conference, Reno, May 2007.
-
(2007)
2007 Electronic Components and Technology Conference
-
-
Lee, B.-W.1
Sundaram, V.2
Wiedenman, B.3
Yoon, C.K.4
Iyer, M.5
Tummala, R.R.6
-
6
-
-
35348899435
-
Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities
-
Reno, May 30-June 2
-
Nithya Sankaran, Baik-Woo Lee, Venky Sundaram, Ege Engin, Mahadevan Iyer, Madhavan Swaminathan and Rao Tummala, "Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities", 2007 Electronic Components and Technology Conference, Reno, May 30-June 2 (2007)
-
(2007)
2007 Electronic Components and Technology Conference
-
-
Sankaran, N.1
Lee, B.-W.2
Sundaram, V.3
Engin, E.4
Iyer, M.5
Swaminathan, M.6
Tummala, R.7
-
7
-
-
84964595998
-
Investigation of plane-to-plane noise coupling through cutout in multilayer power/ground planes
-
Singapore, Dec
-
J. Lee, Y. M. Seng, M. K. Iyer, and J. Kim, "Investigation of plane-to-plane noise coupling through cutout in multilayer power/ground planes," in Proc. 4th Electronics Packaging Technology Conf, Singapore, Dec. 2002, pp. 257-260.
-
(2002)
Proc. 4th Electronics Packaging Technology Conf
, pp. 257-260
-
-
Lee, J.1
Seng, Y.M.2
Iyer, M.K.3
Kim, J.4
-
8
-
-
20444403734
-
-
Junwoo Lee, Student Member, IEEE, Mihai Dragos Rotaru, Member, IEEE, Mahadevan K. Iyer, Senior Member, IEEE, Hyungsoo Kim, and Joungho Kim, Analysis and Suppression of SSN Noise Coupling Between Power/Ground Plane Cavities Through Cutouts in Multilayer Packages and PCBs, IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28, NO. 2, MAY 2005.
-
Junwoo Lee, Student Member, IEEE, Mihai Dragos Rotaru, Member, IEEE, Mahadevan K. Iyer, Senior Member, IEEE, Hyungsoo Kim, and Joungho Kim, "Analysis and Suppression of SSN Noise Coupling Between Power/Ground Plane Cavities Through Cutouts in Multilayer Packages and PCBs", IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 28, NO. 2, MAY 2005.
-
-
-
|